SLLSEQ6A September 2016 – September 2016 ONET1131EC
PRODUCTION DATA.
A simplified block diagram of the ONET1131EC is shown in Functional Block Diagram.
The ONET1131EC consists of a transmitter path, an analog reference block, an analog to digital converter, and a 2-wire serial interface and control logic block with power-on reset.
The transmit path consists of an adjustable input equalizer, a multi-rate CDR and an output modulator driver. The output driver provides a differential output voltage but can be operated in a single-ended mode to reduce the power consumption. Output waveform control, in the form of cross-point adjustment and de-emphasis are available to improve the optical eye mask margin. Bias current for the laser is provided and an integrated automatic power control (APC) loop to compensate for variations in average optical power over voltage, temperature and time is included.
The ONET1131EC contains an analog to digital converter to support transceiver digital diagnostics and can report the supply voltage, laser bias current, laser photodiode current and internal temperature.
The 2-wire serial interface is used to control the operation of the device and read the status of the control registers.
The data signal is applied to an input equalizer by means of the input signal pins DIN+ / DIN–, which provide on-chip differential 100-Ω line termination. The equalizer is enabled by default and can be disabled by setting the transmitter equalizer disable bit TXEQ_DIS = 1 (bit 1 of register 10). Equalization of up to 300 mm (12 inches) of microstrip or stripline transmission line on FR4 printed circuit boards can be achieved. The amount of equalization is set through register settings TXCTLE [0..3] (register 11). The device can accept input amplitude levels from 100 mVpp up to 1000 mVpp.
The clock and data recovery function consists of a Phase-Locked Loop (PLL) and retimer. The CDR can be operated without a reference clock and the Voltage Controlled Oscillator (VCO) can cover 9.8 Gbps to 11.7 Gbps data rates. The PLL is phase locked to the incoming data stream and attenuates the high frequency jitter on the data, producing a recovered clean clock with substantially reduced jitter. An external capacitor for the PLL loop filter is connected to the LF pin. A value of 2.2 nF is recommended. The clean clock is used to retime the incoming data, producing an output signal with reduced jitter, and in effect, resetting the jitter budget for the transmitter.
The CDR is enabled by default. The CDR can be disabled and bypassed by setting the transmitter CDR disable bit TXCDR_DIS = 1 (bit 4 of register 10). Alternatively, the CDR can be left powered on but bypassed by setting the transmitter CDR bypass bit TX_CDRBP = 1 (bit 3 of register 10).
The CDR is designed to meet the XFP Datacom requirements and Telecom requirements for a maximum of 1-dB jitter peaking at a frequency greater than 120 kHz. The CDR is not designed to meet the Telecom regenerator requirements of jitter peaking less than 0.03 dB at a frequency less than 120 kHz. The default CDR bandwidth is typically 4.5 MHz and can be adjusted using the SEL_RES[0..2] bits (bits 5 to 7 of register 51). Adjusting these bits changes the bandwidth of both the transmitter and receiver CDRs.
For the majority of applications, the default settings in register 19 for the transmitter CDR can be used. However, for some applications or for test purposes, some modes of operation may be useful. The frequency detector for the PLL is set to an automatic mode of operation by default. When a signal is applied to the transmitter input the frequency detector search algorithm will be initiated to determine the frequency of the data. The default algorithm ensures a fast CDR lock time of less than 2 ms. The fast lock can be disabled by setting the transmitter CDR fast lock disable bit TXFL_DIS = 1 (bit 3 of register 19). Once the frequency has been detected then the frequency detector will be disabled and the supply current will decrease by approximately 10mA. In some applications, such as when there are long periods of idle data, it may be advantageous to keep the frequency detector permanently enabled by setting the transmitter frequency detector enable bit TXFD_EN = 1 (bit 5 of register 19). For test purposes, the frequency detector can be permanently disabled by setting the transmitter frequency detector disable bit TXFD_DIS = 1 (bit 4 of register 19). For fast lock times the frequency detector can be set to one of two preselected data rates using the transmitter frequency detection mode selection bits TXFD_MOD[0..1] (bits 6 and 7 of register 19). If it is desired to use the retimer at lower data rates than the standard 9.8 to 11.7Gbps then the transmitter divider ratio should be adjusted accordingly through TXDIV[0..2] (bits 0 to 2 of register 19). For example, for re-timed operation at 2.5 Gbps the divider should be set to divide by 4.
The modulation current is sunk from the common emitter node of the limiting output driver differential pair by means of a modulation current generator, which is digitally controlled by the 2-wire serial interface.
The collector nodes of the output stages are connected to the transmitter output pins TXOUT+ and TXOUT–. The collectors have internal 50Ω back termination resistors to VCC_TX. The outputs are optimized to drive a 50 Ω single-ended load and to obtain the maximum single-ended output voltage of 2.0Vpp, AC coupling and inductive pull-ups to VCC are required. For reduced power consumption the DC resistance of the inductive pull-ups should be minimized to provide sufficient headroom on the TXOUT+ and TXOUT– pins.
The polarity of the output pins can be inverted by setting the transmitter output polarity switch bit, TXOUTPOL (bit 5 of register 10) to 1. In addition, the output driver can be disabled by setting the transmitter output driver disable bit TXOUT_DIS = 1 (bit 6 of register 10).
The output driver is set to differential output by default. In order to reduce the power consumption for single-ended applications driving an electroabsorptive modulated laser (EML) the output drive register 13 should be set to single-ended mode. The single-ended output signal is enabled by setting the transmitter mode select bit TXMODE = 1 (bit 6 of register 13). The positive output is active by default. To enable the negative output and disable the positive output set TXOUTSEL = 1 (bit 7 of register 13).
Output de-emphasis can be applied to the signal by adjusting the transmitter de-emphasis bits TXDEADJ[0..3] (bits 0 to 3 of register 13). In addition, the width of the applied de-emphasis can be increased by setting the transmitter output peaking width TXPKSEL = 1 (bit 6 of register 11). The wide peaking width would typically be useful for a more capacitive transmitter load. How de-emphasis is applied is controlled through the TXSTEP bit (bit 5 of register 13). Setting TXSTEP = 1 delays the time of the applied de-emphasis and has more of an impact on the falling edge. A graphical representation of the two de-emphasis modes is shown in Figure 23. Using de-emphasis can help to optimize the transmitted output signal; however, it will add to the power consumption.
The output edge speed can be set to slow mode of operation through the TXSLOW bit (bit 4 of register 13). For transmitter modulation output settings (TXMOD - register 12) below 0xC0 it is recommended to set TXSLOW = 1 to reduce the output jitter.
The modulation current generator provides the current for the high speed output driver described above. The circuit can be digitally controlled through the 2-wire interface block or controlled by applying an analog voltage in the range of 0 to 2 V to the AMP pin. The default method of control is through the 2-wire interface. To use the AMP pin set the transmitter amplitude control bit TXAMPCTRL = 1 (bit 0 of register 10).
An 8-bit wide control bus, TXMOD[0..7] (register 12), is used to set the desired modulation current and the output voltage.
The entire transmitter signal path, including CDR, can be disabled and powered down by setting TX_DIS = 1 (bit 7 of register 10).
The ONET1131EC transmitter has DC offset cancellation to compensate for internal offset voltages. The offset cancellation can be disabled by setting TXOC_DIS = 1 (bit 2 of register 10).
The crossing point can be moved toward the one level by setting TXCPSGN = 1 (bit 7 of register 14) and it can be moved toward the zero level by setting TXCPSGN = 0. The percentage of shift depends upon the register settings of the transmitter cross-point adjustment bits TXCPADJ[0..6] (register 14).
The bias current for the laser is turned off by default and has to be enabled by setting the laser bias current enable bit TXBIASEN = 1 (bit 2 of register 1). In open loop operation, selected by setting TXOLENA = 1 (bit 4 of register 1), the bias current is set directly by the 10-bit wide control word TXBIAS[0..9] (register 15 and register 16). In Automatic Power Control (APC) mode, selected by setting TXOLENA = 0, the bias current depends on the register settings TXBIAS[0..9] and the coupling ratio (CR) between the laser bias current and the photodiode current. CR = IBIAS/IPD. If the photodiode cathode is connected to VCC and the anode is connected to the PD pin (PD pin is sinking current) set TXPDPOL = 1 (bit 0 of register 1). If the photodiode anode is connected to ground and the cathode is connected to the PD pin (PD pin is sourcing current), set TXPDPOL = 0.
Three photodiode current ranges can be selected by means of the photodiode current range bits TXPDRNG[0..1] (bits 5 and 6 of register 1). The photodiode range should be chosen to keep the laser bias control DAC, TXBIAS[0..9], close to the center of its range. This keeps the laser bias current set point resolution high. For details regarding the bias current setting in open-loop mode as well as in closed-loop mode, see the Register Mapping table.
The ONET1131EC has the ability to source or sink the bias current. The default condition is for the BIAS pin to source the current (TXBIASPOL = 0). To act as a sink, set TXBIASPOL = 1 (bit 1 of register 1).
The bias current is monitored using a current mirror with a gain equal to 1/100. By connecting a resistor between MONB and GND, the bias current can be monitored as a voltage across the resistor. A low temperature coefficient precision resistor should be used. The bias current can also be monitored as a 10 bit unsigned digital word by setting the transmitter bias current digital monitor selection bit TXDMONB = 1 (bit 5 of register 16) and removing the resistor from MONB to ground.
The photodiode current is monitored using a current mirror with various gains that are dependent upon the photodiode current range being used. By connecting a resistor between MONP and GND, the photodiode current can be monitored as a voltage across the resistor. A low temperature coefficient precision resistor should be used. The photodiode current can also be monitored as a 10 bit unsigned digital word by setting the transmitter photodiode current digital monitor selection bit TXDMONP = 1 (bit 6 of register 16) and removing the resistor from MONP to ground.
The ONET1131EC provides built in laser safety features. The following fault conditions are detected if the transmitter fault detection enable bit TXFLTEN = 1 (bit 3 of register 1):
If the fault detection is being used then to avoid a fault from occurring at start-up it is recommended to set up the required bias current and APC loop conditions first and enable the laser bias current (TXBIASEN = 1) as the last step in the sequence of commands.
If one or more fault conditions occur and the transmitter fault enable bit TXFLTEN is set to 1, the ONET1131EC responds by:
Fault recovery is performed by the following procedure:
The ONET1131EC is supplied by a single 2.5 V ±5% supply voltage connected to the VCC and VDD pins. This voltage is referred to ground (GND) and can be monitored as a 10 bit unsigned digital word through the 2-wire interface.
On-chip bandgap voltage circuitry generates a reference voltage, independent of the supply voltage, from which all other internally required voltages and bias currents are derived.
In order to minimize the module component count, the ONET1131ECprovides an on-chip temperature sensor. The temperature can be monitored as a 10 bit unsigned digital word through the 2-wire interface.
The ONET1131EC has power on reset circuitry which ensures that all registers are reset to default values during startup. After the power-on to initialize time (tINIT1), the internal registers are ready to be loaded. The part is ready to transmit data after the initialize to transmit time (tINIT2), assuming that the enable chip bit EN_CHIP = 1 (bit 0 of register 0). In addition, the disable pin DIS must be set to zero.
The ONET1131EC bias current can be disabled by setting the DIS pin high. The internal registers are not reset. After the transmitter disable pin DIS is set low the part returns to its prior output settings.
The ONET1131EC has an internal 10 bit analog to digital converter (ADC) that converts the analog monitors for temperature, power supply voltage, bias current and photodiode current into a 10 bit unsigned digital word. The first 8 most significant bits (MSBs) are available in register 40 and the 2 least significant bits (LSBs) are available in register 41. Depending on the accuracy required, 8 bits or 10 bits can be read. However, due to the architecture of the 2-wire interface, in order to read the 2 registers, 2 separate read commands have to be sent.
The ADC is enabled by default so to monitor a particular parameter, select the parameter with ADCSEL[0..2] (bits 0 to 2 of register 3). Table 1 shows the ADCSEL bits and the parameter that is monitored.
ADCSEL2 | ADCSEL1 | ADCSEL0 | MONITORED PARAMETER |
---|---|---|---|
0 | 0 | 0 | Temperature |
0 | 0 | 1 | Supply voltage |
0 | 1 | 0 | Bias current |
0 | 1 | 1 | Photodiode current |
To digitally monitor the photodiode current, ensure that TXDMONP = 1 (bit 6 of register 16) and that a resistor is not connected to the MONP pin. To digitally monitor the bias current, ensure that TXDMONB = 1 (bit 5 of register 16) and that a resistor is not connected to the MONB pin. The ADC is disabled by default. To enable the ADC, set the ADC oscillator enable bit OSCEN = 1 (bit 6 of register 3) and set the ADC enable bit ADCEN = 1 (bit 7 of register 3).
The digital word read from the ADC can be converted to its analog equivalent through the following formulas.
Where: ADCx = the decimal value read from the ADC
The ONET1131EC uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCK, are driven, respectively, by the serial data and serial clock from a microprocessor, for example. The SDA and SCK pins require external 4.7-kΩ to 10-kΩ pull-up resistor to VCC for proper operation.
The 2-wire interface allows write access to the internal memory map to modify control registers and read access to read out the control signals. The ONET1131EC is a slave device only which means that it cannot initiate a transmission itself; it always relies on the availability of the SCK signal for the duration of the transmission. The master device provides the clock signal as well as the START and STOP commands. The protocol for a data transmission is as follows:
Regarding timing, the ONET1131EC is I2C compatible. The typical timing is shown in Figure 2 and a complete data transfer is shown in Figure 24. Parameters for Figure 2 are defined in the Timing Diagram Definitions.
Both SDA and SCK lines remain HIGH
A change in the state of the SDA line, from HIGH to LOW, while the SCK line is HIGH, defines a START condition (S). Each data transfer is initiated with a START condition.
A change in the state of the SDA line from LOW to HIGH while the SCK line is HIGH defines a STOP condition (P). Each data transfer is terminated with a STOP condition; however, if the master still wishes to communicate on the bus, it can generate a repeated START condition and address another slave without first generating a STOP condition.
Only one data byte can be transferred between a START and a STOP condition. The receiver acknowledges the transfer of data.
Each receiving device, when addressed, is obliged to generate an acknowledge bit. The transmitter releases the SDA line and a device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Setup and hold times must be taken into account. When a slave-receiver doesn’t acknowledge the slave address, the data line must be left HIGH by the slave. The master can then generate a STOP condition to abort the transfer. If the slave-receiver does acknowledge the slave address but some time later in the transfer cannot receive any more data bytes, the master must abort the transfer. This is indicated by the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP condition, see Figure 2.
The ONET1131EC has two main functional modes of operation: differential transmitter output and single-ended transmitter output.
Operation with differential output is the default mode of operation. This mode is intended for externally modulated lasers requiring differential drive such as Mach Zehnder modulators.
In order to reduce the power consumption for single-ended EML applications the output driver should be set to single-ended mode. The single-ended output signal can be enabled by setting the transmitter mode select bit TXMODE = 1 (bit 6 of register 13). The positive output is active by default. To enable the negative output and disable the positive output set TXOUTSEL = 1 (bit 7 of register 13).
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GLOBAL SW_PIN RESET | Reserved | I2C RESET | EN_CHIP | ||||
RWSC | RW | RWSC | RWSC | RW |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset. RWSC = Read/Write self clearing (always reads back to zero) |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | GLOBAL SW_PIN RESET | RWSC | 0 | Global Reset SW
1 = reset, resets all I2C and EEPROM modules to default 0 = normal operation (self-clearing, always reads back ‘0’) |
6:3 | Reserved | R/W | 1 | Reserved |
2 | RWSC | 0 | Reserved | |
1 | I2C RESET | RWSC | 0 | Chip reset bit
1 = resets all I2C registers to default 0 = normal operation (self-clearing, always reads back ‘0’) |
0 | EN_CHIP | R/W | 1 | Enable chip bit
1 = Chip enabled 0 = Chip disabled |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXMONPFLT | TXPDRNG1 | TXPDRNG0 | TXOLENA | TXFLTEN | TXBIASEN | TTXBIASPOL | TXPDPOL |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | TXMONPFLT | R/W | 0 | Analog photodiode current monitor fault trigger bit 1 = Fault trigger on MONP pin is enabled 0 = Fault trigger on MONP pin is disabled |
6 5 |
TXPDRNG1 TXPDRNG0 |
R/W | 0 | Photodiode current range bits
1X: up to 3080 μA / 3 μA resolution 01: up to 1540 μA / 1.5 μA resolution 00: up to 770 μA / 0.75 μA resolution |
4 | TXOLENA | R/W | 0 | Open loop enable bit
1 = Open loop bias current control 0 = Closed loop bias current control |
3 | TXFLTEN | R/W | 0 | Fault detection enable bit
1 = Fault detection on 0 = Fault detection off |
2 | TXBIASEN | R/W | 0 | Laser Bias current enable bit
1 = Bias current enabled. Toggle to 0 to reset a fault condition. 0 = Bias current disabled |
1 | TXBIASPOL | R/W | 0 | Laser Bias current polarity bit
1 = Bias pin sinks current 0 = Bias pin sources current |
0 | TXPDPOL | R/W | 0 | Photodiode polarity bit
1 = Photodiode cathode connected to VCC 0 = Photodiode anode connected to GND |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | |||||||
R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | Reserved | R/W | 0 | Reserved |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADCEN | OSCEN | Reserved | ADCRST | Reserved | ADCSEL2 | ADCSEL1 | ADCSEL0 |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | ADCEN | R/W | 0h | ADC enabled bit
1 = ADC enabled 0 = ADC disabled |
6 | OSCEN | R/W | 0h | ADC oscillator bit
1 = Oscillator enabled 0 = Oscillator disabled |
5 | Reserved | R/W | 0h | Reserved |
4 | ADCRST | R/W | 0h | ADC reset
1 = ADC reset 0 = ADC no reset |
3 | Reserved | R/W | 0h | Reserved |
2 | ADCSEL2 | R/W | 0h | ADC input selection bits <2:0>
000 selects the temperature sensor 001 selects the power supply monitor 010 selects IMONB 011 selects IMONP 1XX are reserved |
1 | ADCSEL1 | R/W | 0h | |
0 | ADCSEL0 | R/W | 0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_DIS | TXOUT_DIS | TXOUTPOL | TXCDR_DIS | TX_CDRBP | TXOC_DIS | TXEQ_DIS | TXAMPCTRL |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXAMPRNG | TXPKSEL | TXTCSEL1 | TXTCSEL0 | TXCTLE3 | TXCTLE2 | TXCTLE1 | TXCTLE0 |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | TXAMPRNG | R/W | 0 | TX output AMP range
1 = Half TX output amplitude range 0 = Full TX output amplitude range |
6 | TXPKSEL | R/W | 0 | TX output peaking width
1 = wide peaking width 0 = narrow peaking width |
5 | TXTCSEL1 | R/W | 0 | TXOUT temperature compensation select bit 1 |
4 | TXTCSEL0 | R/W | 0 | TXOUT temperature compensation select bit 0 |
3 | TXCTLE3 | R/W | 0 | TX input CTLE setting
0000 = minimum 1111 = maximum |
2 | TXCTLE2 | R/W | 0 | |
1 | TXCTLE1 | R/W | 0 | |
0 | TXCTLE0 | R/W | 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXMOD7 | TXMOD76 | TXMOD5 | TXMOD4 | TXMOD3 | TXMOD2 | TXMOD1 | TXMOD0 |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | TXMOD7 | R/W | 0 | TX Modulation current setting: sets the output voltage
Output Voltage: 2.4 Vpp / 9.5 mVpp steps |
6 | TXMOD6 | R/W | 0 | |
5 | TXMOD5 | R/W | 0 | |
4 | TXMOD4 | R/W | 0 | |
3 | TXMOD3 | R/W | 0 | |
2 | TXMOD2 | R/W | 0 | |
1 | TXMOD1 | R/W | 0 | |
0 | TXMOD0 | R/W | 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXOUTSEL | TXMODE | TXSTEP | TXSLOW | TXDEADJ3 | TXDEADJ2 | TXDEADJ1 | TXDEADJ0 |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | TXOUTSEL | R/W | 0 | TX output selection bit
1 = The negative output TXOUT– is active 0 = The positive output TXOUT+ is active |
6 | TXMODE | R/W | 0 | TX output mode selection bit
1 = Single-ended mode 0 = Differential mode |
5 | TXSTEP | R/W | 0 | TX output de-emphasis mode selection bit
1 = Delayed de-emphasis 0 = Normal de-emphasis |
4 | TXSLOW | R/W | 0 | TX edge speed selection bit
1 = Slow edge speed 0 = Normal operation |
3 | TXDEADJ3 | R/W | 0 | TX de-emphasis setting
0000 = minimum 1111 = maximum |
2 | TXDEADJ2 | R/W | 0 | |
1 | TXDEADJ1 | R/W | 0 | |
0 | TXDEADJ0 | R/W | 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXCPSGN | TXCPADJ6 | TXCPADJ5 | TXCPADJ4 | TXCPADJ3 | TXCPADJ2 | TXCPADJ61 | TXCPADJ60 |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | TXCPSGN | R/W | 0 | TX Eye cross-point adjustment setting
TXCPSGN = 1 (positive shift) Maximum shift for 1111111 Maximum shift for 1111111 |
6 | TXCPADJ6 | R/W | 0 | |
5 | TXCPADJ5 | R/W | 0 | |
4 | TXCPADJ4 | R/W | 0 | |
3 | TXCPADJ3 | R/W | 0 | |
2 | TXCPADJ2 | R/W | 0 | |
1 | TXCPADJ1 | R/W | 0 | |
0 | TXCPADJ0 | R/W | 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXBIAS9 | TXBIAS8 | TXBIAS7 | TXBIAS6 | TXBIAS5 | TXBIAS4 | TXBIAS3 | TXBIAS2 |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | TXBIAS9 | R/W | 0 | Bias current settings (8MSB; 2LSBs are in register 16)
Closed loop (APC): Coupling ratio CR = IBIAS / IPD, TXBIAS = 0..1023, IBIAS ≤ 150 mA: TXPDRNG = 00; IBIAS = 0.75 μA x CR x TXBIAS TXPDRNG = 01; IBIAS = 1.5 μA x CR x TXBIAS TXPDRNG = 1X; IBIAS = 3 μA x CR x TXBIAS
Open Loop:
|
6 | TXBIAS8 | R/W | 0 | |
5 | TXBIAS7 | R/W | 0 | |
4 | TXBIAS6 | R/W | 0 | |
3 | TXBIAS5 | R/W | 0 | |
2 | TXBIAS4 | R/W | 0 | |
1 | TXBIAS3 | R/W | 0 | |
0 | TXBIAS2 | R/W | 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | TXDMONP | TXDMONB | Reserved | TXBIAS1 | TXBIAS1 | ||
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | Reserved | R/W | 0 | Reserved |
6 | TXDMONP | R/W | 0 | Digital photodiode current monitor selection bit (MONP)
1 = Digital photodiode monitor is active (no external resistor is needed) 0 = Analog photodiode monitor is active (external resistor is required) |
5 | TXDMONB | R/W | 0 | Digital bias current monitor selection bit (MONB)
1 = Digital bias current monitor is active (no external resistor is needed) 0 = Analog bias current monitor is active (external resistor is required) |
4:2 | Reserved | R/W | 0 | Reserved |
1 | TXBIAS1 | R/W | 0 | Laser Bias current setting (2 LSBs) |
0 | TXBIAS0 | R/W | 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXBMF7 | TXBMF6 | TXBMF5 | TXBMF4 | TXBMF3 | TXBMF2 | TXBMF1 | TXBMF0 |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | TXBMF7 | R/W | 0 | Bias current monitor fault threshold
With TXDMONB = 1 Register sets the value of the bias current that will trigger a fault. The external resistor on the MONB pin must be removed to use this feature. |
6 | TXBMF6 | R/W | 0 | |
5 | TXBMF5 | R/W | 0 | |
4 | TXBMF4 | R/W | 0 | |
3 | TXBMF3 | R/W | 0 | |
2 | TXBMF2 | R/W | 0 | |
1 | TXBMF1 | R/W | 0 | |
0 | TXBMF0 | R/W | 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXPMF7 | TXPMF6 | TXPMF5 | TXPMF4 | TXPMF3 | TXPMF2 | TXPMF1 | TXPMF0 |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | TXPMF7 | R/W | 0 | Power monitor fault threshold
With TXDMONP = 1 Register sets the value of the photodiode current that will trigger a fault. The external resistor on the MONP pin must be removed to use this feature. |
6 | TXPMF6 | R/W | 0 | |
5 | TXPMF5 | R/W | 0 | |
4 | TXPMF4 | R/W | 0 | |
3 | TXPMF3 | R/W | 0 | |
2 | TXPMF2 | R/W | 0 | |
1 | TXPMF1 | R/W | 0 | |
0 | TXPMF0 | R/W | 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXFD_MOD1 | TXFD_MOD0 | TXFD_EN | TXFD_DIS | 0TXFL_DIS | TXDIV2 | TXDIV1 | TXDIV0 |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | TXFD_MOD1 | R/W | 0 | TX frequency detection mode selection
00 = auto selection enabled 01 = Pre-selected to 10.3 Gbps 10 = Pre-select to 11.1 Gbps 11 = test mode (do not use) |
6 | TXFD_MOD0 | R/W | 0 | |
5 | TXFD_EN | R/W | 0 | TX frequency detector enable bit
1 =TX frequency detector is always enabled 0 = TX frequency detector in automatic mode |
4 | TXFD_DIS | R/W | 0 | TX frequency detector disable bit
1 = TX frequency detector is always disabled 0 = TX frequency detector is in automatic mode |
3 | TXFL_DIS | R/W | 0 | TX CDR fast lock disable bit
1 = TX CDR fast lock disabled 0 = TX CDR in fast lock mode |
2 | TXDIV2 | R/W | 0 | TX Divider Ratio
000: Full-Rate, 001: Divide by 2 010: Divide by 4 011: Divide by 8 100: Divide by 16 101: Divide by 32 |
1 | TXDIV1 | R/W | 0 | |
0 | TXDIV0 | R/W | 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | |||||||
R |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | Reserved | R | 0 | Reserved |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADC9 | ADC8 | ADC5 | ADC4 | ADC3 | ADC2 | ADC1 | ADC0 |
R | R | R | R | R | R | R | R |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | ADC9 (MSB) | R | 0 |
Digital representation of the ADC input source (read only) |
6 | ADC8 | R | 0 | |
5 | ADC7 | R | 0 | |
4 | ADC6 | R | 0 | |
3 | ADC5 | R | 0 | |
2 | ADC4 | R | 0 | |
1 | ADC3 | R | 0 | |
0 | ADC2 | R | 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | ADC1 | ADC0 | |||||
R | R | R |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | Resereved | R | 0h | Reserved |
1 | ADC1 | R | 0h | Digital representation of the ADC input source (read only) |
0 | ADC0 (LSB) | R | 0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXCDRLock | TXCDRLock | TX_FLT | TX_DRVDIS | Reserved | |||
R | R | R | R | R |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; RCLR = Read clear |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | TXCDRLock | R | 0 | TX CDR lock status bit
1 = TX CDR is not locked 0 = TX CDR is locked |
6 | TXCDRLock (latched Low) | RCLR | 0 | Latched low status of bit 7. Cleared when read. Latched low bit set to 0 when raw status goes low and keep it low even if raw status goes high. |
5 | TX_FLT | R | 0 | TX fault status bit
1 = TX fault detected 0 = TX fault not detected |
4 | TX_DRVDIS | R | 0 | TX driver disable status bit
1 = TX fault logic disables the driver 0 = TX fault logic does not disable the driver |
3:0 | Reserved | R | 0 | Reserved |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | |||||||
R |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | Reserved | R | 0 | Reserved |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL_RES_2 | SEL_RES_1 | SEL_RES_0 | Reserved | ||||
R | R | R | R |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SEL_RES_2 | R/W | 0 | CDR Loop Filter Resistor
000: 75, 001: 150 010: 225 011: 300 100: 375 101: 450 110: 525 111: 600 Default = 225 |
6 | SEL_RES_1 | R/W | 1 | |
5 | SEL_RES_0 | R/W | 0 | |
4:0 | Reserved | R/W | 0 | Reserved |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | |||||||
R |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | Reserved | R | 0 | Reserved |