SLLSEQ6A September   2016  – September 2016 ONET1131EC

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Function
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Timing Diagram Definitions
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Equalizer
      2. 7.3.2 CDR
      3. 7.3.3 Modulator Driver
      4. 7.3.4 Modulation Current Generator
      5. 7.3.5 DC Offset Cancellation and Cross Point Control
      6. 7.3.6 Bias Current Generation and APC Loop
      7. 7.3.7 Laser Safety Features and Fault Recovery Procedure
      8. 7.3.8 Analog Block
        1. 7.3.8.1 Analog Reference and Temperature Sensor
        2. 7.3.8.2 Power-On Reset
        3. 7.3.8.3 Analog to Digital Converter
          1. 7.3.8.3.1 Temperature
          2. 7.3.8.3.2 Power Supply Voltage
          3. 7.3.8.3.3 Photodiode Current Monitor
          4. 7.3.8.3.4 Bias Current Monitor
        4. 7.3.8.4 2-Wire Interface and Control Logic
        5. 7.3.8.5 Bus Idle
        6. 7.3.8.6 Start Data Transfer
        7. 7.3.8.7 Stop Data Transfer
        8. 7.3.8.8 Data Transfer
      9. 7.3.9 Acknowledge
    4. 7.4 Device Functional Modes
      1. 7.4.1 Differential Transmitter Output
      2. 7.4.2 Single-Ended Transmitter Output
    5. 7.5 Programming
    6. 7.6 Register Mapping
      1. 7.6.1 R/W Control Registers
        1. 7.6.1.1 Core Level Register 0 (offset = 0100 0001 [reset = 41h]
        2. 7.6.1.2 Core Level Register 1 (offset = 0000 0000) [reset = 0h]
        3. 7.6.1.3 Core Level Register 2 (offset = 0000 0000 ) [reset = 0h]
        4. 7.6.1.4 Core Level Register 3 (offset = 0000 0000) [reset = 0h]
      2. 7.6.2 TX Registers
        1. 7.6.2.1  TX Register 10 (offset = 0000 0000) [reset = 0h]
        2. 7.6.2.2  TX Register 11 (offset = 0000 0000) [reset = 0h]
        3. 7.6.2.3  TX Register 12 (offset = 0000 0000) [reset = 0h]
        4. 7.6.2.4  TX Register 13 (offset = 0h) [reset = 0]
        5. 7.6.2.5  TX Register 14 (offset = 0000 0000) [reset = 0h]
        6. 7.6.2.6  TX Register 15 (offset = 0000 0000) [reset = 0h]
        7. 7.6.2.7  TX Register 16 (offset = 0000 0000) [reset = 0h]
        8. 7.6.2.8  TX Register 17 (offset = 0000 0000) [reset = 0h]
        9. 7.6.2.9  TX Register 18 (offset = 0000 0000) [reset = 0h]
        10. 7.6.2.10 TX Register 19 (offset = 0000 0000) [reset = 0h]
      3. 7.6.3 Reserved Registers
        1. 7.6.3.1 Reserved Registers 20-39
      4. 7.6.4 Read Only Registers
        1. 7.6.4.1 Core Level Register 40 (offset = 0000 0000) [reset = 0h]
        2. 7.6.4.2 Core Level Register 41 (offset = 0000 0000) [reset = 0h]
        3. 7.6.4.3 TX Register 43 (offset = 0000 0000) [reset = 0h]
      5. 7.6.5 Adjustment Registers
        1. 7.6.5.1 Adjustment Registers 44-50
        2. 7.6.5.2 Adjustment Register 51 (offset = 0100 0000) [reset = 40h]
        3. 7.6.5.3 Adjustment Registers 52-55
  8. 8 Application Information and Implementations
    1. 8.1 Application Information
    2. 8.2 Typical Application, Transmitter Differential Mode
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
      4. 8.2.4 Typical Application, Transmitter Single-Ended Mode
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
        3. 8.2.4.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings (1)(2)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage at VCC, VDD –0.5 3 V
Voltage at 3.3-V tolerant pins LOL, SDA, SCK, FLT, DIS –0.5 3.6 V
at all other pins MONB, DIN+, DIN–, PD, MONP, LF, BIAS, OUT–, OUT+, AMP, COMP –0.5 3 V
Maximum current at transmitter input pins DIN+, DIN– 10 mA
Maximum current at transmitter output pins OUT+, OUT– 125 mA
Maximum junction temperature, TJ 125 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
VCC Supply Voltage 2.37 2.5 2.63 V
VIH Digital input high voltage DIS, SCK, SDA, 3.3-V tolerant IOs 2 V
VIL Digital input low voltage 0.8 V
Photodiode current range Control bit TXPDRNG = 1x, step size = 3 µA 3080 µA
Control bit TXPDRNG = 01, step size = 1.5 µA 1540
Control bit TXPDRNG = 00, step size = 0.75 µA 770
Serial Data rate TXCDR_DIS = 0 9.8 11.7 Gbps
TXCDR_DIS = 1 1 11.7
VAMP Amplitude control input voltage range 0 2 V
tR(IN) Input rise time 20%–80% 30 45 ps
tF(IN) Input fall time 20%–80% 30 45 ps
TC Temperature at thermal pad –40 100 °C

6.4 Thermal Information

THERMAL METRIC(1) RSM (VQFN) UNIT
32 PINS
RθJA Junction-to-ambient thermal resistance 37.2 °C/W
RθJCtop Junction-to-case (top) thermal resistance 30.1 °C/W
RθJB Junction-to-board thermal resistance 7.8 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 7.6 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance 2.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 DC Electrical Characteristics

Over recommended operating conditions, open loop operation, VOUT = 2 VPP single-ended, I(BIAS) = 80 mA, unless otherwise noted. Typical operating condition is at VCC = 2.5 V and TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC Supply voltage 2.37 2.5 2.63 V
IVCC Supply current in single-ended TX mode with CDRs enabled TXMODE = 1, TXCDR_DIS = 0, TX VOUT = 2 VPP single-ended, I(BIAS) = 0 mA 158 193 mA
Power dissipation in single-ended TX mode with CDRs enabled 380 508 mW
Supply current in differential TX mode with CDRs enabled TXMODE = 0, TXCDR_DIS = 0, TX VOUT = 2 VPP single-ended, I(BIAS) = 0 mA 197 237 mA
Power dissipation in differential TX mode with CDRs enabled 493 623 mW
Supply current in single-ended TX mode with CDRs disabled TXMODE = 1, TXCDR_DIS = 1, TX VOUT = 2 VPP single-ended, I(BIAS) = 0 mA 119 193 mA
Power dissipation in single-ended TX mode with CDRs disabled 298 376 mW
Supply current in differential TX mode with CDRs disabled TXMODE = 0, TXCDR_DIS = 1, TX VOUT = 2 VPP single-ended, I(BIAS) = 0 mA; 164 200 mA
Power dissipation in differential TX mode with CDRs disabled 410 526 mW
R(IN) Data input resistance Differential between DIN+ / DIN– 100 Ω
Data input termination mismatch 5%
R(OUT) Ooutput resistance Single-ended at OUT+ or OUT– 60 Ω
Digital input current DIS pull up to VCC –20 20 µA
VOH Digital output high voltage LOL, FLT pull-up to VCC,
ISOURCE = 37.5 μA		 2.1 V
VOL Digital output low voltage LOL, FLT pull-up to VCC,
ISINK = 350 μA		 0.4 V
I(BIAS-MIN) Minimum bias current See (1) 5 mA
I(BIAS-MAX) Maximum bias current Source. BIASPOL = 0, DAC set to maximum, open and closed loop 145 150 mA
Sink. BIASPOL = 1, DAC set to maximum, open and closed loop 95 100 mA
I(BIAS-DIS) Bias current during disable 100 µA
Average power stability APC loop enabled ±0.5 dB
Bias pin compliance voltage Source. TXBIASPOL = 0 VCC - 0.45 V
Sink. TXBIASPOL = 1 0.45 V
Temperature sensor accuracy With 1-point external mid-scale calibration ±3 °C
V(PD) Photodiode reverse bias voltage APC active, I(PD) = 1500 μA 1.3 2.3 V
Photodiode fault current level Percent of target I(PD) (2) 150%
Photodiode current monitor ratio I(MONP) / I(PD) with control bit PDRNG = 1X 10% 12.5% 15%
I(MONP) / I(PD) with control bit PDRNG = 01 20% 25% 30%
I(MONP) / I(PD) with control bit TXPDRNG = 00 40% 50% 60%
Monitor diode DMI accuracy With external mid-scale calibration –15% 15%
Bias current monitor ratio I(MONB) / I(BIAS) (nominal 1/100 = 1%), V(MONB) < 1.5V 0.9% 1% 1..1%
Bias current DMI accuracy I(BIAS) ≥ 20 mA –15% 15%
Power supply monitor accuracy With external mid-scale calibration –2% 2%
VCC(RST) VCC reset threshold voltage VCC voltage level which triggers power-on reset 1.8 2.1 V
VCC(RSTHYS) VCC reset threshold voltage hysteresis 100 mV
V(MONB-FLT) Fault voltage at MONB TXFLTEN = 1, TXDMONB = 0, Fault occurs if voltage at MONB exceeds this value 1.15 1.2 1.25 V
V(MONP-FLT) Fault voltage at MONP TXFLTEN = 1, TXMONPFLT = 1, TXDMONP = 0, Fault occurs if voltage at MONP exceeds this value 1.15 1.2 1.25 V
(1) The bias current can be set below the specified minimum according to the corresponding register setting; however, in closed loop operation settings below the specified value may trigger a fault.
(2) Specified by design over process, supply and temperature variation

6.6 AC Electrical Characteristics

Over recommended operating conditions, open loop operation, VOUT = 2 VPP single-ended, I(BIAS) = 80 mA unless otherwise noted. Typical operating condition is at VCC = 2.5 V and TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TX INPUT SPECIFICATIONS
CDR lock range CPRI, Ethernet, SONET, Fibre Channel 9.80 11.7 Gbps
SDD11 Differential input return loss 0.05 GHz < f ≤ 0.1 GHz 20 dB
0.1 GHz < f ≤ 5.5 GHz 12 15
5.5 GHz < f < 12 GHz 8
SDD11 Differential to common mode conversion 0.1 GHz < f < 12 GHz 10 15 dB
SDD11 Common mode input return loss 0.1 GHz < f < 12 GHz 3 dB
Input AC common mode voltage tolerance 15 mV
Total Non-DDJ Total jitter less ISI 0.45 UIPP
T(JTX) Total Jitter 0.65 UIPP
S(JTX) Sinusoidal Jitter Tolerance With addition of input jitter, See Figure 1 UIPP
VIN Differential input voltage swing 100 1000 mVPP
EQ(boost) EQ high freq boost Maximum setting; 7 GHz 6 9 dB
TX OUTPUT SPECIFICATIONS
Differential output return loss 0.01 GHz < f < 12 GHz 12 dB
VO(MIN) Minimum output amplitude AC Coupled Outputs, 50-Ω single-ended load 0.5 VPP
TX OUTPUT SPECIFICATIONS in SINGLE-ENDED MODE of OPERATION (TXMODE = 1)
VO(MAX) Maximum output amplitude AC Coupled Outputs, 50-Ω load, single-ended 2 VPP
Output amplitude stability AC Coupled Outputs, 50-Ω load, single-ended 230 mVPP
High Cross Point Control Range 50-Ω load, single-ended 70% 75%
Low Cross Point Control Range 50-Ω load, single-ended 35% 40%
Cross Point Stability 50-Ω load, single-ended -5 5 pp
Output de-emphasis TXDEADJ[0..3] = 1111, TXPKSEL = 0 5 dB
TXDEADJ[0..3] = 1111, TXPKSEL = 1 6
TX OUTPUT SPECIFICATIONS in DIFFERENTIAL MODE of OPERATION (TXMODE = 0)
VO(MAX) Maximum output amplitude AC Coupled Outputs, 100-Ω differential load 3.6 VPP
Output amplitude stability AC Coupled Outputs, 100-Ω differential load 230 mVPP
High Cross Point Control Range 100-Ω differential load 65% 75%
Low Cross Point Control Range 100-Ω differential load 35% 40%
Cross Point Stability 100-Ω differential load –5 5 pp
Output de-emphasis TXDEADJ[0..3] = 1111, TXPKSEL = 0 5 dB
TXDEADJ[0..3] = 1111, TXPKSEL = 1 6
CDR SPECIFICATIONS
BW(TX) Jitter Transfer Bandwidth 9.95 Gbps, PRBS31 8 MHz
J(PTX) Jitter Peaking > 120 kHz 1 dB
JGEN(rms) Random RMS jitter generation Clock pattern, 50 kHz to 80 MHz 6 mUIrms
JGEN(PP) Total jitter generation Clock pattern, 50 kHz to 80 MHz, BER = 10-12 60 mUIPP

6.7 Timing Requirements

Over recommended operating conditions, typical operating condition is at VCC = 2.5 V and TA = 25°C
MIN TYP MAX UNIT
t(APC) APC time constant CAPC 0.01 µF, IPD = 500 µA, PD coupling ratio CR = 150,
PDRNG = 01		 50 µs
t(INIT1) Power-on to initialize Power-on to registers ready to be loaded 0.2 1 ms
t(INIT2) Initialize to transmit Register load STOP command to part ready to transmit valid data 2 ms
t(OFF) Transmitter disable time Rising edge of DIS to I(BIAS) ≤ 0.1 × I(BIAS-NOMINAL) 1 5 µs
t(ON) Disable negate time Falling edge of DIS to I(BIAS) ≥ 0.9 × I(BIAS-NOMINAL) 1 ms
t(RESET) DIS pulse width Time DIS must held high to reset part 100 ns
t(FAULT) Fault assert time Time from fault condition to FLT high 50 µs
OUTPUT SPECIFICATIONS in SINGLE-ENDED MODE of OPERATION (TXMODE = 1)
tR(OUTTX) Output rise time 20% - 80%, AC Coupled Outputs, 50-Ω load, single-ended 30 42 ps
tF(OUTTX) Output fall time 20% - 80%, AC Coupled Outputs, 50-Ω load, single-ended 30 42 ps
ISI(TX) Intersymbol interference TXEQ_DIS = 1, 11.3 Gbps, PRBS9 pattern, 150-mVpp,
600-mVpp, 1200-mVpp differential input voltage		 4 12 ps
TXEQ_DIS = 0, 11.3 Gbps, PRBS9 pattern, 150-mVpp,
600-mVpp, 1200-mVpp differential input voltage, maximum equalization with 18-inch transmission line at the input.		 7
R(JTX) Serial data output random jitter 0.4 0.75 psRMS
Output de-emphasis width TXPKSEL = 0 28 ps
TXPKSEL = 1 35
OUTPUT SPECIFICATIONS in DIFFERENTIAL MODE of OPERATION (TXMODE = 0)
tR(OUTTX) Output rise time 20%–80%, AC Coupled Outputs, 100-Ω differential load 30 42 ps
tF(OUTTX) Output fall time 20%–80%, AC Coupled Outputs, 100-Ω differential load 30 42 ps
ISI(TX) Intersymbol interference TXEQ_DIS = 1, 11.3 Gbps, PRBS9 pattern, 150-mVpp,
600-mVpp, 1200-mVpp differential input voltage		 4 10 ps
TXEQ_DIS = 0, 11.3 Gbps, PRBS9 pattern, 150-mVpp,
600-mVpp, 1200-mVpp differential input voltage, maximum equalization with 18-inch transmission line at the input.		 7
R(JTX) Serial data output random jitter 0.4 0.75 psRMS
Output Peaking Width TXPKSEL = 0 28 ps
TXPKSEL = 1 35
CDR SPECIFICATIONS
t(Lock,TX) CDR Acquisition time 2 ms
LOL assert time 500 μs
ONET1131EC Transmitter_Input_Sinusoidal_Jitter_sllsej3.gif Figure 1. Input Sinusoidal Jitter Tolerance (INF-8077i Rev. 4.5 XFP MSA)
ONET1131EC I2C_Timing_Diag_SLLSEJ3.gif Figure 2. 2-Wire Interface Diagram

6.8 Timing Diagram Definitions

MIN TYP MAX UNIT
fSCK SCK clock frequency 400 kHz
tBUF Bus free time between START and STOP conditions 1.3 µs
tHDSTA Hold time after repeated START condition. After this period, the first clock pulse is generated 0.6 µs
tLOW Low period of the SCK clock 1.3 µs
tHIGH High period of the SCK clock 0.6 µs
tSUSTA Setup time for a repeated START condition 0.6 µs
tHDDAT Data HOLD time 0 µs
tSUDAT Data setup time 100 ns
tR Rise time of both SDA and SCK signals 300 ns
tF Fall time of both SDA and SCK signals 300 ns
tSUSTO Setup time for STOP condition 0.6 µs

6.9 Typical Characteristics

Typical operating condition is at VCC = 2.5 V, TA = 25°C, VOUT = 2 VPP Single-ended, DIN = 600 mVPP differential, CDR enabled (unless otherwise noted).
ONET1131EC D010_SLLSEJ3.gif
TXMODE = 0
Figure 3. Deterministic Jitter vs Modulation Current
ONET1131EC D012_SLLSEJ3.gif
TXMODE = 0
Figure 5. Deterministic Jitter vs Temperature
ONET1131EC D014_SLLSEJ3.gif
TXMODE = 1
Figure 7. Random Jitter vs Modulation Current
ONET1131EC D016_SLLSEJ3.gif
TXMODE = 1
Figure 9. Rise-Time and Fall-Time vs Modulation Current
ONET1131EC D018_SLLSEJ3.gif
Figure 11. Source Bias Current in Open Loop Mode vs Bias Register Setting
ONET1131EC D020_SLLSEJ3.gif
Figure 13. Bias-Monitor Current I(MONB) vs Bias Current
ONET1131EC D022_SLLSEJ3.gif
TXMODE = 0
Figure 15. Output Voltage vs Modulation Current
ONET1131EC D024_SLLSEJ3.gif
TXMODE = 0 Bias Current = 0
Figure 17. Supply Current vs Temperature
ONET1131EC D026_SLLSEJ3.gif
Figure 19. Bias Current Monitor Fault vs TXBMF Register Setting
ONET1131EC Eye_Diagram_ TXMODE0_SLLSEJ3.png
TXMODE = 0 15 ps/Div
Figure 21. Eye-Diagram at 11.3 Gbps
ONET1131EC D011_SLLSEJ3.gif
TXMODE = 1
Figure 4. Deterministic Jitter vs Modulation Current
ONET1131EC D013_SLLSEJ3.gif
TXMODE = 1
Figure 6. Deterministic Jitter vs Temperature
ONET1131EC D015_SLLSEJ3.gif
TXMODE = 1
Figure 8. Random Jitter vs Temperature
ONET1131EC D017_SLLSEJ3.gif
TXMODE = 1
Figure 10. Rise-Time and Fall-Time vs Temperature
ONET1131EC D019_SLLSEJ3.gif
Figure 12. Sink Bias Current in Open Loop Mode vs Bias Register Setting
ONET1131EC D021_SLLSEJ3.gif
TXPDRNG[0..1] = 00
Figure 14. Photodiode-Monitor Current I(MONP) vs PD Current
ONET1131EC D023_SLLSEJ3.gif
TXMODE = 1
Figure 16. Output Voltage vs Modulation Current
ONET1131EC D025_SLLSEJ3.gif
TXMODE = 1 Bias Current = 0
Figure 18. Supply Current vs Temperature
ONET1131EC D027_SLLSEJ3.gif
Figure 20. Photodiode Current Monitor Fault vs TXPMF Register Setting
ONET1131EC Eye_Diagram_ TXMODE1_SLLSEJ3.png
TXMODE = 1 15 ps/Div
Figure 22. Eye-Diagram at 11.3 Gbps