SBOS516G September   2010  – May 2020 OPA171 , OPA2171 , OPA4171

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Offset Voltage vs Common-Mode Voltage
      2.      Offset Voltage vs Power Supply
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions: OPA171
    2.     Pin Functions: OPA2171
    3.     Pin Functions: OPA4171
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA171
    5. 6.5 Thermal Information: OPA2171
    6. 6.6 Thermal Information: OPA4171
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Characteristics
      2. 7.3.2 Common-Mode Voltage Range
      3. 7.3.3 Phase-Reversal Protection
      4. 7.3.4 Capacitive Load and Stability
    4. 7.4 Device Functional Modes
      1. 7.4.1 Common-Mode Voltage Range
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Electrical Overstress
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Capacitive Load and Stability
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Electrical Characteristics

at TA = 25°C, VS = 2.7 to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage 0.25 ±1.8 mV
Over temperature TA = –40°C to +125°C 0.3 ±2 mV
dVOS/dT Drift TA = –40°C to +125°C 0.3 ±2 µV/°C
vs power supply VS = 4 to 36 V
TA = –40°C to +125°C		 1 ±3 µV/V
Channel separation, DC DC 5 µV/V
INPUT BIAS CURRENT
IB Input bias current ±8 ±15 pA
Over temperature TA = –40°C to +125°C ±3.5 nA
IOS Input offset current ±4 pA
Over temperature TA = –40°C to +125°C ±3.5 nA
NOISE
Input voltage noise f = 0.1 Hz to 10 Hz 3 µVPP
en Input voltage noise density f = 100 Hz 25 nV/√Hz
f = 1 kHz 14 nV/√Hz
INPUT VOLTAGE
VCM Common-mode voltage range(1) (V–) – 0.1 V (V+) – 2 V V
CMRR Common-mode rejection ratio VS = ±2 V
(V–) – 0.1 V < VCM < (V+) – 2 V
TA = –40°C to +125°C		 90 104 dB
VS = ±18 V
(V–) – 0.1 V < VCM < (V+) – 2 V
TA = –40°C to +125°C		 104 120 dB
INPUT IMPEDANCE
Differential 100 || 3 MΩ || pF
Common-mode 6 || 3 1012Ω || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 4 V to 36 V
(V–) + 0.35 V < VO < (V+) – 0.35 V
TA = –40°C to +125°C		 110 130 dB
FREQUENCY RESPONSE
GBP Gain bandwidth product 3 MHz
SR Slew rate G = 1 1.5 V/µs
tS Settling time To 0.1%
VS = ±18 V, G = 1
10-V step		 6 µs
To 0.01% (12 bit)
VS = ±18 V, G = 1
10-V step		 10 µs
Overload recovery time VIN × gain > VS 2 µs
THD+N Total harmonic distortion + noise G = 1, f = 1 kHz
VO = 3 VRMS 		0.0002%
OUTPUT
VO Voltage output swing from rail VS = 5 V
RL = 10 kΩ		 30 mV
Over temperature RL = 10 kΩ
AOL ≥ 110 dB
TA = –40°C to +125°C		 (V–) + 0.35 (V+) – 0.35 V
ISC Short-circuit current +25/–35 mA
CLOAD Capacitive load drive See Typical Characteristics pF
RO Open-loop output resistance f = 1 MHz
IO = 0 A		 150 Ω
POWER SUPPLY
VS Specified voltage range 2.7 36 V
IQ Quiescent current per amplifier IO = 0 A 475 595 µA
Over temperature IO = 0 A
TA = –40°C to +125°C		 650 µA
TEMPERATURE
Specified range –40 125 °C
Operating range –55 150 °C
(1) The input range can be extended beyond (V+) – 2 V up to V+. See Typical Characteristics and Application and Implementation for additional information.

Table 1. Characteristic Performance Measurements

DESCRIPTION FIGURE
Offset Voltage Production Distribution Figure 1
Offset Voltage Drift Distribution Figure 2
Offset Voltage vs Temperature Figure 3
Offset Voltage vs Common-Mode Voltage Figure 4
Offset Voltage vs Common-Mode Voltage (Upper Stage) Figure 5
Offset Voltage vs Power Supply Figure 6
IB and IOS vs Common-Mode Voltage Figure 7
Input Bias Current vs Temperature Figure 8
Output Voltage Swing vs Output Current (Maximum Supply) Figure 9
CMRR and PSRR vs Frequency (Referred-to Input) Figure 10
CMRR vs Temperature Figure 11
PSRR vs Temperature Figure 12
0.1-Hz to 10-Hz Noise Figure 13
Input Voltage Noise Spectral Density vs Frequency Figure 14
THD+N Ratio vs Frequency Figure 15
THD+N vs Output Amplitude Figure 16
Quiescent Current vs Temperature Figure 17
Quiescent Current vs Supply Voltage Figure 18
Open-Loop Gain and Phase vs Frequency Figure 19
Closed-Loop Gain vs Frequency Figure 20
Open-Loop Gain vs Temperature Figure 21
Open-Loop Output Impedance vs Frequency Figure 22
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 23, Figure 24
No Phase Reversal Figure 25
Positive Overload Recovery Figure 26
Negative Overload Recovery Figure 27
Small-Signal Step Response (100 mV) Figure 28, Figure 29
Large-Signal Step Response Figure 30, Figure 31
Large-Signal Settling Time (10-V Positive Step) Figure 32
Large-Signal Settling Time (10-V Negative Step) Figure 33
Short-Circuit Current vs Temperature Figure 34
Maximum Output Voltage vs Frequency Figure 35
Channel Separation vs Frequency Figure 36