SBOS900B September   2018  – June 2019 OPA2156

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Low Input Voltage Noise Spectral Density
      2.      OPA2156 Transimpedance Configuration
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA2156
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Phase Reversal Protection
      2. 7.3.2 Electrical Overstress
      3. 7.3.3 Thermal Considerations
      4. 7.3.4 Thermal Shutdown
      5. 7.3.5 Common-Mode Voltage Range
      6. 7.3.6 Overload Recovery
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Slew Rate Limit for Input Protection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Dissipation
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI (Free Software Download)
        2. 11.1.1.2 TI Precision Designs
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at TA = 25°C, VS = ±2.25V to ±18V, VCM =VOUT = VS / 2, and RL = 2 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage, PMOS   ±25 ±200 µV
TA = –40°C to +85°C ±300 µV
TA = –40°C to +125°C See Typical Characteristics
VOS Input offset voltage, NMOS VCM = (V+) – 1.25 V ±0.25 ±3 mV
VCM = (V+) – 1.25 V, TA = –40°C to +125°C (SOIC) ±5 mV
VCM = (V+) – 1.25 V, TA = –40°C to +105°C (MSOP)
dVOS/dT Input offset voltage drift PMOS, SOIC TA = –40°C to +125°C ±0.5 ±3 µV/°C
PMOS, MSOP TA = –40°C to +105°C
NMOS, VCM = (V+) – 1.25 V TA = –40°C to +125°C ±1
PSRR Power-supply rejection ratio ±0.3 ±4.5 µV/V
TA = –40°C to +125°C (SOIC) ±5
TA = –40°C to +105°C (MSOP)
INPUT BIAS CURRENT
IB Input bias current SOIC ±5 ±40 pA
MSOP ±5 ±80 pA
TA = –40°C to +85°C (SOIC) ±1.5 nA
TA = –40°C to +85°C (MSOP) ±15 nA
TA = –40°C to +125°C See Typical Characteristics nA
IOS Input offset current ±2 ±40 pA
TA = –40°C to +85°C (SOIC) ±1.5 nA
TA = –40°C to +85°C (MSOP) ±2.5 nA
TA = –40°C to +125°C See Typical Characteristics nA
NOISE
En Input voltage noise (V–) < VCM < (V+) – 2.25 V f = 0.1 Hz to 10 Hz 1.9 µVPP
(V+) – 1.25 V < VCM < (V+) f = 0.1 Hz to 10 Hz 3.4
en Input voltage noise density (V–) < VCM < (V+) – 2.25 V f = 100 Hz 12.0 nV/√Hz
f = 1 kHz 4
f = 10 kHz 3.0
en Input voltage noise density (V+) – 1.25 V < VCM < (V+) f = 100 Hz 13.0
f = 1 kHz 9.7
f = 10 kHz 4.0
in Input current noise density f = 1 kHz 19 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage range (V–) – 0.1 (V+) + 0.1 V
CMRR Common-mode rejection ratio, PMOS (V–) < VCM < (V+) – 2.25 V, VS = ±18 V 106 120 dB
CMRR Common-mode rejection ratio, PMOS TA = –40°C to +125°C (SOIC) 100
CMRR Common-mode rejection ratio, PMOS TA = –40°C to +105°C (MSOP)
CMRR Common-mode rejection ratio, NMOS (V+) – 1.25 V < VCM < (V+), VS = ±18 V 82 120
CMRR Common-mode rejection ratio, NMOS TA = –40°C to +125°C (SOIC) 74
CMRR Common-mode rejection ratio, NMOS TA = –40°C to +105°C (MSOP)
INPUT IMPEDANCE
ZID Differential 100 || 9.1 MΩ || pF
ZIC Common-mode 6 || 1.9 1012Ω || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 0.6 V < VO < (V+) – 0.6 V, VS = ±18 V (SOIC) 130 154 dB
(V–) + 0.6 V < VO < (V+) – 0.6 V, VS = ±18 V (MSOP) 128 154
TA = –40°C to +85°C 126
FREQUENCY RESPONSE
GBW Unity gain bandwidth 20 MHz
Gain bandwidth product G = 100 25 MHz
SR Slew rate VS = ±18 V, G = –1, 10-V step 40 V/µs
ts Settling time To 0.01%, CL = 20 pF VS = ±18 V, G = –1, 10-V step 600 ns
tOR Overload recovery time G = –10 100 ns
THD+N Total harmonic distortion + noise G = 1, f = 1 kHz, VO = 3.5 VRMS –132 dB
0.000025%
G = 1, f = 20 kHz, VO = 3.5 VRMS –126 dB
0.00005%
Crosstalk dc 150 dB
f = 100 kHz 120 dB
OUTPUT
VO Voltage output swing from power supply 200 250 mV
ISC Short-circuit current VS = ±18 V 100 mA
CL Capacitive load drive See Typical Characteristics pF
ZO Open-loop output impedance f = 1 MHz, IO = 0 A 25 Ω
POWER SUPPLY
IQ Quiescent current per amplifier IO = 0 A 4.4 5.2 mA
TA = –40°C to +125°C (SOIC) 5.2 mA
TA = –40°C to +105°C (MSOP) mA
TEMPERATURE
Thermal protection 170 °C
Thermal hysteresis 15 °C