SBOS406G June   2007  – December 2015 OPA2376 , OPA376 , OPA4376

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA376
    5. 6.5 Thermal Information: OPA2376
    6. 6.6 Thermal Information: OPA4376
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Input Offset Voltage and Input Offset Voltage Drift
      3. 7.3.3 Capacitive Load and Stability
      4. 7.3.4 Common-Mode Voltage Range
      5. 7.3.5 Input and ESD Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Basic Amplifier Configurations
      2. 8.1.2 Active Filtering
      3. 8.1.3 Driving an Analog-to-Digital Converter
      4. 8.1.4 Phantom-Powered Microphone
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Detailed Design Procedure
      2. 8.2.2 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Photosensitivity
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI™ (Free Software Download)
        2. 11.1.1.2 TI Precision Designs
        3. 11.1.1.3 WEBENCH® Filter Designer
    2. 11.2 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

  • Noise can propagate into analog circuitry through the power pins of the circuit as a whole, and the op amp itself. Bypass capacitors can reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
    • Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply applications.
  • Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat, and reduces EMI noise pickup. Physically separate the digital and analog grounds, paying attention to the flow of the ground current. For more detailed information refer to Circuit Board Layout Techniques, SLOA089.
  • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is better than opposed to in parallel with the noisy trace.
  • Place the external components as close to the device as possible. As shown in Figure 32, keeping RF and RG close to the inverting input minimizes parasitic capacitance.
  • Keep the length of the input traces as short as possible. The input traces are the most sensitive part of the circuit.
  • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.
  • Clean the PCB following board assembly for best performance.
  • Any precision-integrated circuit may experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

10.1.1 Photosensitivity

Although the OPA2376YZD package has a protective backside coating that reduces the amount of light exposure on the die, unless fully shielded, ambient light can reach the active region of the device. Input bias current for the package is specified in the absence of light. Depending on the amount of light exposure in a given application, an increase in bias current, and possible increases in offset voltage, should be expected. Fluorescent lighting may introduce noise or hum because of the time-varying light output. Best layout practices include end-product packaging that provides shielding from possible light sources during operation.

10.2 Layout Example

OPA376 OPA2376 OPA4376 layout_example_sbos406.gif Figure 32. Layout Example