SLES177B Data sheet

SLES177B April 2006 – August 2015 PCM1808

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

PW|14
- MPDS360

Thermal pad, mechanical data (Package|Pins)

PW|14
- QFND305D

Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted) ⁽¹⁾

			MIN	MAX	UNIT
V_CC	Analog supply voltage		–0.3	6.5	V
V_DD	Digital supply voltage		–0.3	4	V
	Ground voltage differences	AGND, DGND		±0.1	V
	Digital input voltage	LRCK, BCK, DOUT	–0.3	(V_DD + 0.3 V) < 4	V
	Digital input voltage	SCKI, MD0, MD1, FMT	–0.3	6.5	V
V_INL, V_INR, V_REF	Analog input voltage		–0.3	(V_CC + 0.3 V) < 6.5	V
	Input current (any pins except supplies)			±10	mA
T_J	Junction temperature			150	°C
T_stg	Storage temperature		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±4000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
V_CC	Analog supply voltage (see Power Supply Recommendations)		4.5	5	5.5	V
V_DD	Digital supply voltage		2.7	3.3	3.6	V
	Analog input voltage, full scale (–0 dB)	V_CC = 5 V			3	Vp-p
V_IH ⁽¹⁾	High input logic level		2		V_DD	VDC
V_IL ⁽¹⁾	Low input logic level		0		0.8	VDC
V_IH ⁽²⁾ ⁽³⁾	High input logic level		2		5.5	VDC
V_IL ⁽²⁾ ⁽³⁾	Low input logic level		0		0.8	VDC
	Digital input logic family		TTL compatible
	Digital input clock frequency, system clock		2.048		49.152	MHz
	Digital input clock frequency, sampling clock		8		96	kHz
	Digital output load capacitance				20	pF
T_A	Operating ambient temperature range		–40		85	°C
T_J	Junction temperature				150	°C

(1) Pins 7, 8: LRCK, BCK (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, in slave mode)

(2) Pin 6: SCKI (Schmitt-trigger input, 5-V tolerant)

(3) Pins 10–12: MD0, MD1, FMT (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, 5-V tolerant)

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		PCM1808	UNIT
		PW (TSSOP)
		14 PINS
R_θJA	Junction-to-ambient thermal resistance	89.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	25.6	°C/W
R_θJB	Junction-to-board thermal resistance	30.3	°C/W
ψ_JT	Junction-to-top characterization parameter	1.4	°C/W
ψ_JB	Junction-to-board characterization parameter	29.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

All specifications at T_A = 25°C, V_CC = 5 V, V_DD = 3.3 V, master mode, f_S = 48 kHz, system clock = 512 f_S, 24-bit data, unless otherwise noted

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
	Resolution			24		Bits
DATA FORMAT
	Audio data interface format		I²S, left-justified
	Audio data bit length			24		Bits
	Audio data format		MSB-first, 2s complement
f_S	Sampling frequency		8	48	96	kHz
	System clock frequency	256 f_S	2.048	12.288	24.576	MHz
		384 f_S	3.072	18.432	36.864
		512 f_S	4.096	24.576	49.152
INPUT LOGIC
V_IH ⁽¹⁾	High input logic level		2		V_DD	VDC
V_IL ⁽¹⁾	Low input logic level		0		0.8	VDC
V_IH ⁽²⁾ ⁽³⁾	High input logic level		2		5.5	VDC
V_IL ⁽²⁾ ⁽³⁾	Low input logic level		0		0.8	VDC
I_IH ⁽²⁾	High input logic current	V_IN = V_DD			±10	µA
I_IL ⁽²⁾	Low input logic current	V_IN = 0 V			±10	µA
I_IH ⁽¹⁾ ⁽³⁾	High input logic current	V_IN = V_DD		65	100	µA
I_IL ⁽¹⁾ ⁽³⁾	Low input logic current	V_IN = 0 V			±10	µA
OUTPUT LOGIC
V_OH ⁽⁴⁾	High output logic level	I_OUT = –4 mA	2.8			VDC
V_OL ⁽⁴⁾	Low output logic level	I_OUT = 4 mA			0.5	VDC
DC ACCURACY
	Gain mismatch, channel-to-channel			±1	±3	% of FSR
	Gain error			±3	±6	% of FSR
DYNAMIC PERFORMANCE ⁽⁵⁾
THD+N	Total harmonic distortion + noise	V_IN = –0.5 dB, f_S = 48 kHz		–93	–87	dB
		V_IN = –0.5 dB, f_S = 96 kHz ⁽⁶⁾		–87
		V_IN = –60 dB, f_S = 48 kHz		–37
		V_IN = –60 dB, f_S = 96 kHz ⁽⁶⁾		–39
	Dynamic range	f_S = 48 kHz, A-weighted	95	99		dBVDC
	Dynamic range	f_S = 96 kHz, A-weighted ⁽⁶⁾		101		dBVDC
S/N	Signal-to-noise ratio	f_S = 48 kHz, A-weighted	95	99		dB
S/N	Signal-to-noise ratio	f_S = 96 kHz, A-weighted ⁽⁶⁾		101		dB
	Channel separation	f_S = 48 kHz	93	97		dB
	Channel separation	f_S = 96 kHz ⁽⁶⁾		91		dB
ANALOG INPUT
	Input voltage			0.6 V_CC		Vp-p
	Center voltage (V_REF)			0.5 V_CC		V
	Input impedance			60		kΩ
	Antialiasing filter frequency response	–3 dB		1.3		MHz
DIGITAL FILTER PERFORMANCE
	Pass band				0.454 f_S	Hz
	Stop band		0.583 f_S			Hz
	Pass-band ripple				±0.05	dB
	Stop-band attenuation		–65			dB
	Delay time			17.4 / f_S
	HPF frequency response	–3 dB		0.019 f_S / 1000
POWER SUPPLY REQUIREMENTS
I_CC	Analog supply current ⁽⁷⁾	f_S = 48 kHz, 96 kHz ⁽⁶⁾		8.6	11	mA
I_CC	Analog supply current ⁽⁷⁾	Powered down ⁽⁸⁾		1		μA
I_DD	Digital supply current ⁽⁷⁾	f_S = 48 kHz		5.9	8	mA
		f_S = 96 kHz ⁽⁶⁾		10.2		mA
		Powered down ⁽⁸⁾		150		µA
	Power dissipation ⁽⁷⁾	f_S = 48 kHz		62	81	mW
		f_S = 96 kHz ⁽⁶⁾		77		mW
		Powered down ⁽⁸⁾		500		µW

(1) Pins 7, 8: LRCK, BCK (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, in slave mode)

(2) Pin 6: SCKI (Schmitt-trigger input, 5-V tolerant)

(3) Pins 10–12: MD0, MD1, FMT (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, 5-V tolerant)

(4) Pins 7–9: LRCK, BCK (in master mode), DOUT

(5) Testing of analog performance specifications uses an audio measurement system by Audio Precision™ with 400-Hz HPF and 20-kHz LPF in RMS mode.

(6) f_S = 96 kHz, system clock = 256 f_S.

(7) Minimum load on LRCK (pin 7), BCK (pin 8), DOUT (pin 9)

(8) Power-down and reset functions enabled by halting SCKI, BCK, LRCK.

6.6 Timing Requirements

		MIN	NOM	MAX	UNIT
SYSTEM CLOCK TIMING
t_w(SCKH)	System clock pulse duration, HIGH	8			ns
t_w(SCKL)	System clock pulse duration, LOW	8			ns
	System clock duty cycle	40%		60%
CLOCK-HALT POWER-DOWN AND RESET TIMING
t_(CKR)	Delay time from SCKI halt to internal reset	4			µs
t_(RST)	Delay time from SCKI resume to reset release			1024 SCKI	µs
t_(REL)	Delay time from reset release to DOUT output			8960 / f_S	µs
AUDIO DATA INTERFACE TIMING (Slave Mode: LRCK and BCK Work as Inputs)⁽¹⁾
t_(BCKP)	BCK period	1 / (64 f_S)			ns
t_(BCKH)	BCK pulse duration, HIGH	1.5 × t_(SCKI)			ns
t_(BCKL)	BCK pulse duration, LOW	1.5 × t_(SCKI)			ns
t_(LRSU)	LRCK setup time to BCK rising edge	50			ns
t_(LRHD)	LRCK hold time to BCK rising edge	10			ns
t_(LRCP)	LRCH period	10			µs
t_(CKDO)	Delay time, BCK falling edge to DOUT valid	–10		40	ns
t_(LRDO)	Delay time, LRCK edge to DOUT valid	–10		40	ns
t_r	Rise time of all signals			20	ns
t_f	Fall time of all signals			20	ns
AUDIO DATA INTERFACE TIMING (Master Mode: LRCK and BCK Work as Outputs)⁽²⁾
t_(BCKP)	BCK period	150	1 / (64 f_S)	2000	ns
t_(BCKH)	BCK pulse duration, HIGH	65		1200	ns
t_(BCKL)	BCK pulse duration, LOW	65		1200	ns
t_(CKLR)	Delay time, BCK falling edge to LRCK valid	–10		20	ns
t_(LRCP)	LRCK period	10	1 / f_S	125	ns
t_(CKDO)	Delay time, BCK falling edge to DOUT valid	–10		20	ns
t_(LRDO)	Delay time, LRCK edge to DOUT valid	–10		20	ns
t_r	Rise time of all signals			20	ns
t_f	Fall time of all signals			20	ns
AUDIO CLOCK INTERFACE TIMING (Master Mode: BCK Work as Outputs)⁽³⁾
t_(SCKBCK)	Delay time, SCKI rising edge to BCK edge	5		30	ns

(1) Timing measurement reference level is 1.4 V for input and 0.5 V_DD for output. Rise and fall times are from 10% to 90% of the input-output signal swing. Load capacitance of DOUT is 20 pF. t_(SCKI) is the SCKI period.

(2) Timing measurement reference level is 0.5 V_DD. Rise and fall times are from 10% to 90% of the input-output signal swing. Load capacitance of all signals is 20 pF.

(3) Timing measurement reference level is 1.4 V for input and 0.5 V_DD for output. Load capacitance of BCK is 20 pF. This timing applies when SCKI frequency is less than 25 MHz.