SLLSFE2 June 2019 SN65HVDA1040B-Q1
PRODUCTION DATA.
During normal mode (the only mode in which the CAN driver is active) the TXD dominant time-out circuit prevents the transceiver from blocking network communication in event of a hardware or software failure where TXD is held dominant longer than the time-out period tDST. The dominant time-out circuit is triggered by a falling edge on TXD. If no rising edge is seen before the time-out constant of the circuit expires (tDST), the CAN bus driver is disabled, thus freeing the bus for communication between other network nodes. The CAN driver is re-activated when a recessive signal is seen on the TXD pin, thus clearing the dominant state time-out. The CAN bus pins are biased to recessive level during a TXD dominant state time-out and SPLIT remains on.
NOTE
The maximum dominant TXD time allowed by the TXD Dominant state time-out limits the minimum possible data rate of the device. The CAN protocol allows a maximum of 11 successive dominant bits (on TXD) for the worst case, where 5 successive dominant bits are followed immediately by an error frame. This, along with the t(dom) minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/t(dom)