SCLS252N October   1995  – February 2018 SN54AHCT240 , SN74AHCT240

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Noise Characteristics
    8. 6.8 Operating Characteristics
  7. 7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Related Links
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DB|20
  • NS|20
  • N|20
  • DW|20
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Parameter Measurement Information

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

  • PRR ≤ 1 MHz
  • ZO = 50 Ω
  • tr ≤ 3 ns
  • tf ≤ 3 ns

NOTE

All parameters and waveforms are not applicable to all devices.

SN54AHCT240 SN74AHCT240 scl252n-load-circuit-for-totem-pole-outputs.gif
1. CL includes probe and jig capacitance.
2. The outputs are measured one at a time, with one transition per measurement.
Figure 2. Load Circuit For Totem-Pole Outputs
SN54AHCT240 SN74AHCT240 scl252n-load-circuit-for-3-state-and-open-drain-outputs.gif
1. CL includes probe and jig capacitance.
2. The outputs are measured one at a time, with one transition per measurement.
Figure 3. Load Circuit For Tri-State And Open-Drain Outputs

Table 1. Loading Conditions For Parameter

TEST S1
tPLH(1), tPHL(1) Open
tPLZ(3), tPZL(2) VCC
tPHZ(3), tPZH(2) GND
Open drain VCC
(1) tPLH and tPHL are the same as tpd.
(2) tPZL and tPZH are the same as ten.
(3) tPLZ and tPHZ are the same as tdis.
SN54AHCT240 SN74AHCT240 scl252n-voltage-waveforms-pulse-duration.gifFigure 4. Voltage Waveforms Pulse Durations
SN54AHCT240 SN74AHCT240 scl252n-voltage-waveforms-propagation-delay-times-inverting-and-noninverting-outputs.gif
1. The outputs are measured one at a time, with one transition per measurement.
Figure 5. Voltage Waveforms Propagation Delay Times Inverting and Noninverting Outputs
SN54AHCT240 SN74AHCT240 scl252n-voltage-and-waveforms-setup-and-hold-times.gifFigure 6. Voltage Waveforms Setup And Hold Times
SN54AHCT240 SN74AHCT240 scl252n-voltage-waveforms-enable-and-disable-times-low-and-high-level-enabling.gif
1. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
2. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
3. The outputs are measured one at a time, with one transition per measurement.
Figure 7. Votlage Waveforms Enable And Disable Times Low- and High-Level Enabling