SCES596G JULY 2004 – August 2017 SN74AUP1G126
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see AUP – The Lowest-Power Family and Excellent Signal Integrity ).
This bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is low. This device has the input-disable feature, which allows floating input signals.
To assure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
|PART NUMBER||PACKAGE||BODY SIZE (NOM)|
|SN74AUP1G126DRL||SOT-5X3 (5)||1.60 mm × 1.20 mm|
|SN74AUP1G126DBV||SOT-23 (5)||1.60 mm × 2.90 mm|
|SN74AUP1G126DCK||SC70 (5)||1.25 mm × 2.00 mm|
|SN74AUP1G126DRY||SON (6)||1.00 mm × 1.45 mm|
|SN74AUP1G126DSF||SON (6)||1.00 mm × 1.00 mm|
|SN74AUP1G126YFP||DSBGA (6)||0.76 mm × 1.16 mm|
|SN74AUP1G126YZP||DSBGA (5)||0.89 mm × 1.39 mm|
|SN74AUP1G126DPW||X2SON (5)||0.80 mm × 0.80 mm|
Changes from F Revision (May 2010) to G Revision