SCES882E
December 2017 – December 2023
SN74AXC1T45
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
5.7
Operating Characteristics: TA = 25°C
5.8
Typical Characteristics
6
Parameter Measurement Information
6.1
Load Circuit and Voltage Waveforms
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 0.65-V to 3.6-V Power-Supply Range
7.3.2
I/Os with Integrated Static Pull-Down Resistors
7.3.3
Support High-Speed Translation
7.3.4
Ioff Supports Partial-Power-Down Mode Operation
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.1.1
Enable Times
8.2
Typical Applications
8.2.1
Unidirectional Logic Level-Shifting Application
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curve
8.2.2
Bidirectional Logic Level-Shifting Application
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.3
Application Curve
8.3
Power Supply Recommendations
8.3.1
Power-Up Considerations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DEA|6
MPSS107B
DCK|6
MPDS114C
DRL|6
MPDS159F
DTQ|6
MUSS003
DBV|6
MPDS026O
Thermal pad, mechanical data (Package|Pins)
DCK|6
QFND228B
Orderable Information
sces882e_oa
sces882e_pm
Data Sheet
SN74AXC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation