SCLS094E December   1982  – December 2015 SN54HC74 , SN74HC74

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • DB|14
  • PW|14
  • N|14
  • NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

N, NS, D, DB, PW, J, or W Package
14-Pin PDIP, SO, SOIC, SSOP, TSSOP, CDIP, or CFP
Top View
SN54HC74 SN74HC74 po_scls094.gif
FK Package
20-Pin LCCC
Top View
SN54HC74 SN74HC74 po_scls094_1.gif
NC – No internal connection

Pin Functions

PIN I/O DESCRIPTION
NAME LCCC SOIC, SSOP, CDIP, PDIP, SO, TSSOP, CFP NO.
1CLK 4 3 I Clock input
1CLR 2 1 I Clear input - Pull low to set 1Q output low
1D 3 2 I Input
1PRE 6 4 I Preset input
1Q 8 5 O Output
1Q 9 6 O Inverted output
2CLK 16 11 I Clock input
2CLR 19 13 I Clear input - Pull low to set 1Q output low
2D 18 12 I Input
2PRE 14 10 I Preset input
2Q 13 9 O Output
2Q 12 8 O Inverted output
GND 10 7 Ground
NC 1 No connect (no internal connection)
5
7
11
15
17
VCC 20 14 Supply