SLLSE81A March   2011  – March 2016 SN75LVCP600S

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Equalization
      2. 8.3.2 Auto Low-Power (ALP) Mode (see )
      3. 8.3.3 Out-Of-Band (OOB) Support
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Single 3.3-V Supply
  • Suitable to Receive 6-Gbps Data Over up to >40 Inches (1 m) of FR4 PCB
  • Two-Level RX and TX Equalization
    • RX→ 7, 15 dB
    • TX→ 0, –1.3 dB
  • Pin-Selectable SATA/SAS Signaling
  • Programmable Squelch Threshold for Long Channels
  • Low Power in Active, Partial, and Slumber States
    • 106 mW Typical (Active Mode at 6 Gbps)
    • <11 mW (When Link in Partial and Slumber State)
  • Ultra-small Package for Optimal Placement
    • 10-Pad 2.5-mm × 2.5-mm QFN
  • High ESD-Transient Protection
    • HBM: 9,000 V
    • CDM: 1,500 V
    • MM: 200 V

2 Applications

  • Notebook and Desktop PCs
  • Docking Stations
  • Active Cable
  • Servers
  • Workstations

3 Description

The SN75LVCP600S is a single-channel SATA/SAS signal conditioner supporting data rates up to 6 Gbps. The device complies with SATA physical spec rev 3.0 and SAS electrical spec 2.0. The SN75LVCP600S operates from a single 3.3-V supply and has 100-Ω line termination with a self-biasing feature, making the device suitable for AC coupling. The inputs incorporate an out-of-band (OOB) detector, which automatically squelches the output while maintaining a stable common-mode voltage compliant to the SATA/SAS link.

The SN75LVCP600S handles interconnect losses at its input with selectable equalization settings that can be programmed to the match loss in the channel. For data rates of 3 Gbps and lower, the LVCP600S equalizes signals for a span of up to 50 inches of FR4 board material. For data rates of 6 Gbps, the device compensates >40 inches (1 m) of FR4 material. Rx/Tx equalization level is controlled by the setting of signal control pins EQ and DE.

The device is hot-plug capable (requires use of AC-coupling capacitors at differential inputs and outputs), preventing device damage during device hot-insertion such as async signal plug/removal, unpowered plug/removal, powered plug/removal, or surprise plug/removal.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN75LVCP600S SON (10) 2.50 mm x 2.50 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

SN75LVCP600S typ_app_llse81.gif

4 Revision History

Changes from * Revision (March 2011) to A Revision

  • Added Device Information table, ESD Ratings table, Timing Requirements table, Parameter Measurement Information section, Detailed Description section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support, Mechanical, Packaging, and Orderable InformationGo
  • Changed pins TX+ and TX- I/O Type From: I, CML To: O, VMLGo
  • Changed pins TX+ and TX- Description From: "Non-inverting and inverting CML differential outputs." To: "Noninverting and inverting VML differential outputs."Go
  • Deleted last bullet list item "The control pin pullup and pulldown resistors..." from the Layout Guidelines section Go