SLLSET1B January   2016  – February 2017 SN75LVPE802

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
      1. 7.8.1 Jitter and VOD results: Case 1 at 6 Gbps
      2. 7.8.2 Jitter and VOD Results: Case 2 at 3 Gbps
      3. 7.8.3 Jitter and VOD Results: Case 3 at 1.5 Gbps
      4. 7.8.4 Jitter and VOD Results: Case 4 at 8 Gbps
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  SATA Express
      2. 8.3.2  Receiver Termination
      3. 8.3.3  Receiver Internal Bias
      4. 8.3.4  Input Equalization
      5. 8.3.5  OOB/Squelch
      6. 8.3.6  Auto Low Power
      7. 8.3.7  Transmitter Output Signal
      8. 8.3.8  Transmitter Common Mode
      9. 8.3.9  De-Emphasis
      10. 8.3.10 Transmitter Termination
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Power Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical SATA Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Equalization Configuration
      3. 9.2.3 De-emphasis Configuration
      4. 9.2.4 Application Curves
        1. 9.2.4.1 SN75LVPE802 Equalization Settings for Various Input Trace Length
        2. 9.2.4.2 SN75LVCP802 De-emphasis Settings For various Output Trace Lengths
    3. 9.3 SATA Express Applications
      1. 9.3.1 Detailed Design Procedure
      2. 9.3.2 PCIe Applications
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RTJ|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

RTJ Package
20 Pin (WQFN)
Top View
SN75LVPE802 pinout_sllset1.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
Control Pins
DE1(1) 9 I, LVCMOS Selects de-emphasis settings for CH 1 and CH 2 per Table 1.
Internally tied to VCC / 2.
DE2(1) 8 I, LVCMOS
DEW1 16 I, LVCMOS De-emphasis width control for CH 1 and CH 2.
0 = De-emphasis pulse duration, short
1 = De-emphasis pulse duration, long (default)
DEW2 6 I, LVCMOS
EN 7 I, LVCMOS Device enable and disable pin, internally pulled to VCC.
0 = Device in standby mode
1 = Device enabled (default)
EQ1(1) 17 I, LVCMOS Select equalization settings for CH 1 and CH 2 per Table 1.
Internally tied to VCC / 2.
EQ2(1) 19 I, LVCMOS
High Speed Differential I/O
RX1N 2 I, CML Non-inverting and inverting CML differential input for CH 1 and CH 2. These pins connect to an internal voltage bias via a dual termination resistor circuit.
RX1P 1 I, CML
RX2N 12 I, CML
RX2P 11 I, CML
TX1N 14 O, VML Non-inverting and inverting VML differential input for CH 1 and CH 2. These pins connect to an internal voltage bias via a dual termination resistor circuit.
TX1P 15 O, VML
TX2N 4 O, VML
TX2P 5 O, VML
POWER
GND 3, 13, 18 Power Supply ground
VCC 10, 20 Power Positive supply must be 3.3V ± 10%
(1) Internally biased to VCC / 2 with >200-Ωk pullup or pulldown. When 3-state pins are left as NC, board leakage at the pin pad must be < 1 µA; otherwise, drive to VCC / 2 to assert mid-level state.