SLOS814D March 2014 – September 2016 TAS5421-Q1
The TAS5421-Q1 is a mono analog-input audio amplifier for use in the automotive environment. The design uses an ultra-efficient class-D technology developed by Texas Instruments, but with features added for the automotive industry. The class-D technology allows for reduced power consumption, reduced heat, and reduced peak currents in the electrical system. The device realizes an audio sound system design with smaller size and lower weight than traditional class-AB solutions.
The TAS5421-Q1 device has seven core design blocks:
The differential input stage of the amplifier cancels common-mode noise that appears on the inputs. For a differential audio source, connect the positive lead to IN_P and the negative lead to IN_N. The inputs must be ac-coupled to minimize the output dc-offset and ensure correct ramping of the output voltages. For good transient performance, the impedance seen at each of the two differential inputs should be the same.
The gain setting impacts the analog input impedance of the amplifier. See Table 1 for typical values.
|20 dB||60 kΩ ± 20%|
|26 dB||30 kΩ ± 20%|
|32 dB||15 kΩ ± 20%|
|36 dB||9 kΩ ± 20%|
The PWM converts the analog signal from the preamplifier into a switched signal of varying duty cycle. This is the critical stage that defines the class-D architecture. In the TAS5421-Q1, the modulator is an advanced design with high bandwidth, low noise, low distortion, and excellent stability.
The pulse-width modulation scheme allows increased efficiency at low power. Each output is switching from 0 V to PVDD. The OUTP and OUTN pins are in phase with each other with no input so that there is little or no current in the speaker. The duty cycle of OUTP is greater than 50% and the duty cycle OUTN is less than 50% for positive output voltages. The duty cycle of OUTN is greater than 50% and the duty cycle of OUTP is less than 50% for negative output voltages. The voltage across the load is at 0 V through most of the switching period, reducing power loss.
The gate driver accepts the low-voltage PWM signal and level-shifts the signal to drive a high-current, full-bridge, power FET stage. The device uses proprietary techniques to optimize EMI and audio performance.
The BTL output comprises four matched N-channel FETs for high efficiency and maximum power transfer to the load. By design, the FETs withstand large voltage transients during a load-dump event.
The device incorporates load diagnostic circuitry designed for detecting and determining the status of output connections. The device supports the following diagnostics:
The device reports the presence of any of the short or open conditions to the system via I2C register read.
The device communicates with the system processor via the I2C serial communication bus as an I2C slave-only device. The processor can poll the device via I2C to determine the operating status. All reports of fault conditions and detections are via I2C. The system can also set numerous features and operating conditions via I2C. The I2C interface is active approximately 1 ms after the STANDBY pin is high.
The I2C interface controls the following device features:
The device has a bidirectional serial control interface that is compatible with the Inter IC (I2C) bus protocol and supports 400-kbps data transfer rates for random and sequential write and read operations. This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The master device uses the I2C control interface to program the registers of the device and to read device status.
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data transfer on the bus is serial, one bit at a time. The transfer of address and data is in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, the receiving device acknowledges each byte transferred on the bus with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is HIGH to indicate start and stop conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. Figure 13 shows these conditions. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The device holds SDA LOW during the acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. The address for each device is a unique 7-bit slave address plus a R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. The SDA and SCL signals require the use of an external pullup resistor to set the HIGH level for the bus. There is no limit on the number of bytes that the communicating devices can transmit between start and stop conditions. After transfer of the last word, the master generates a stop condition to release the bus.
To communicate with the device, the I2C master uses addresses shown in Figure 13. Transmission of read and write data can be by single-byte or multiple-byte data transfers.
As shown in Figure 14, a single-byte data-write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address and the read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address byte corresponding to the internal memory address being accessed. After receiving the address byte, the device again responds with an acknowledge bit. Next, the master device transmits the data byte for writing to the memory address being accessed. After receiving the data byte, the device again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.
As shown in Figure 15, a single-byte data-read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data-read transfer, the master device performs both a write and a following read. Initially, the master device performs a write to transfer the address byte of the internal memory address to be read. As a result, the read/write bit is a 0. After receiving the address and the read/write bit, the device responds with an acknowledge bit. In addition, after sending the internal memory address byte, the master device transmits another start condition followed by the device address and the read/write bit again. This time, the read/write bit is a 1, indicating a read transfer. After receiving the address and the read/write bit, the device again responds with an acknowledge bit. Next, the device transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data-read transfer.
A sequential data-read transfer is identical to a single-byte data-read transfer except that the TAS5421-Q1 transmits multiple data bytes to the master device as shown in Figure 16. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte and automatically increments the I2C subaddress by one. After receiving the last data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the transfer.
Three discrete hardware pins are available for real-time control and indication of device status.
Automotive-level EMI performance depends on both careful integrated-circuit design and good system-level design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the design.
The design has minimal parasitic inductances due to the short leads on the package, which dramatically reduces the EMI that results from current passing from the die to the system PCB. The design incorporates circuitry that optimizes output transitions that cause EMI.
The following tables list operating modes and faults.
|Load diagnostic||DC biased||Active||Active|
|Fault and mute||Hi-Z, floating||Active||Active|
|Play||Switching with audio||Active||Active|
|POR||Voltage fault||All||Not applicable||Hard mute (no ramp)||Standby||Self-clearing|
|UV or OV||I2C + FAULT pin||Hi-Z|
|Load dump(1)||FAULT pin|
|OTSD||Thermal fault||Hi-Z, mute, play||I2C + FAULT pin|
|OC fault||Output channel fault||Play|
|Load diagnostic - short||Diagnostic||Hi-Z||None||Hi-Z, re-run diagnostics|
|Load diagnostic - open||I2C||None||Clears on next diagnostic cycle|
|DESCRIPTION||FIXED ADDRESS||READ/WRITE BIT||I2C ADDRESS|
|0x01||R||Latched fault register|
|0x02||R||Status and load diagnostics register|
|0||0||0||0||0||0||0||0||No protection-created faults, default value|
|–||–||–||–||–||1||–||–||A load-diagnostics fault has occurred.|
|–||–||–||–||1||–||–||–||Overcurrent shutdown has occurred.|
|–||–||–||1||–||–||–||–||PVDD undervoltage has occurred.|
|–||–||1||–||–||–||–||–||PVDD overvoltage has occurred.|
|–||1||–||–||–||–||–||–||DC offset protection has occurred.|
|1||–||–||–||–||–||–||–||Overtemperature shutdown has occurred.|
|0||0||0||0||0||0||0||0||No speaker-diagnostic-created faults, default value|
|–||–||–||–||–||–||–||1||Output short to PVDD is present.|
|–||–||–||–||–||–||1||–||Output short to ground is present.|
|–||–||–||–||–||1||–||–||Open load is present.|
|–||–||–||–||1||–||–||–||Shorted load is present.|
|–||–||–||1||–||–||–||–||In a fault condition|
|–||–||1||–||–||–||–||–||Performing load diagnostics|
|–||1||–||–||–||–||–||–||In mute mode|
|1||–||–||–||–||–||–||–||In play mode|
|0||1||1||1||1||0||0||0||26-dB gain, switching frequency set to 400 kHz , SpeakerGuard protection circuitry disabled|
|–||–||–||–||–||–||–||1||Switching frequency set to 500 khz|
|–||–||1||1||0||–||–||–||SpeakerGuard protection circuitry set to 14-V peak output|
|–||–||1||0||1||–||–||–||SpeakerGuard protection circuitry set to 11.8-V peak output|
|–||–||1||0||0||–||–||–||SpeakerGuard protection circuitry set to 9.8-V peak output|
|–||–||0||1||1||–||–||–||SpeakerGuard protection circuitry set to 8.4-V peak output|
|–||–||0||1||0||–||–||–||SpeakerGuard protection circuitry set to 7-V peak output|
|–||–||0||0||1||–||–||–||SpeakerGuard protection circuitry set to 5.9-V peak output|
|–||–||0||0||0||–||–||–||SpeakerGuard protection circuitry set to 5-V peak output|
|0||0||–||–||–||–||–||–||Gain set to 20 dB|
|1||0||–||–||–||–||–||–||Gain set to 32 dB|
|1||1||–||–||–||–||–||–||Gain set to 36 dB|