SLAS965D September 2013 – October 2018 TAS5766M , TAS5768M
PRODUCTION DATA.
Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
---|---|---|---|---|---|---|---|---|---|
33 | 0x21 | DLRK7 | DLRK6 | DLRK5 | DLRK4 | DLRK3 | DLRK2 | DLRK1 | DLRK0 |
Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
DLRK[7:0] | Master Mode LRCK Divider | ||||||||
These bits set the I2S master BCK clock divider value to generate I2S master LRCK clock. | |||||||||
Default value: 00000000 | |||||||||
00000000: Divide by 1 | |||||||||
00000001: Divide by 2 | |||||||||
... | |||||||||
11111111: Divide by 256 |