| RSV |
Reserved |
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Reserved. Do not access. |
| IDFS |
Ignore FS Detection |
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This bit controls whether to ignore the FS detection. When ignored, FS error will not cause a clock error. |
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Default value: 0 |
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0: Regard FS detection |
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1: Ignore FS detection |
| IDBK |
Ignore BCK Detection |
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This bit controls whether to ignore the BCK detection against LRCK. The BCK must be stable between 32FS and 256FS inclusive or an error will be reported. When ignored, a BCK error will not cause a clock error. |
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Default value: 0 |
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0: Regard BCK detection |
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1: Ignore BCK detection |
| IDSK |
Ignore SCK Detection |
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This bit controls whether to ignore the SCK detection against LRCK. Only some certain SCK ratios within some error margin are allowed. When ignored, an SCK error will not cause a clock error. |
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Default value: 0 |
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0: Regard SCK detection |
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1: Ignore SCK detection |
| IDCH |
Ignore Clock Halt Detection |
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This bit controls whether to ignore the SCK halt (static or frequency is lower than acceptable) detection. When ignored an SCK halt will not cause a clock error. |
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Default value: 0 |
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0: Regard SCK halt detection |
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1: Ignore SCK halt detection |
| IDCM |
Ignore LRCK/BCK Missing Detection |
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This bit controls whether to ignore the LRCK/BCK missing detection. The LRCK/BCK need to be in low state (not only static) to be deemed missing. When ignored an LRCK/BCK missing will not cause the DAC go into powerdown mode. |
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Default value: 0 |
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0: Regard LRCK/BCK missing detection |
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1: Ignore LRCK/BCK missing detection |
| DCAS |
Disable Clock Divider Autoset |
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This bit enables or disables the clock auto set mode. When dealing with uncommon audio clock configuration, the auto set mode must be disabled and all clock dividers must be set manually. Addtionally, some clock detectors might also need to be disabled. |
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Default value: 0 |
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0: Enable clock auto set |
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1: Disable clock auto set |
| IPLK |
Ignore PLL Lock Detection |
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This bit controls whether to ignore the PLL lock detection. When ignored, PLL unlocks will not cause a clock error. The PLL lock flag at Page 0 / Register 4, bit 4 is always correct regardless of this bit. |
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Default value: 0 |
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0: PLL unlocks raise clock error |
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1: PLL unlocks are ignored |