SLOS318I May   2000  – August 2015 THS4130 , THS4131

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Tables
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Resistor Matching
      2. 9.1.2 Driving a Capacitive Load
      3. 9.1.3 Data Converters
      4. 9.1.4 Single-Supply Applications
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Active Antialias Filtering
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 General PowerPAD Design Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Resistor Matching

Resistor matching is important in fully-differential amplifiers. The balance of the output on the reference voltage depends on matched ratios of the resistor. CMRR, PSRR, and cancellation of the second-harmonic distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to keep the performance optimized.

VOCM sets the dc level of the output signals. If no voltage is applied to the VOCMpin, it is set to the midrail voltage internally defined as:

Equation 8. THS4130 THS4131 Q1_los318.gif

In the differential mode, the VOCM on the two outputs cancel each other. Therefore, the output in the differential mode is the same as the input in the gain of 1. VOCM has a high bandwidth capability up to the typical operation range of the amplifier. For the prevention of noise going through the device, use a 0.1 µF capacitor on the VOCM pin as a bypass capacitor. TheFunctional Block Diagram shows the simplified diagram of the THS413x.

9.1.2 Driving a Capacitive Load

Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS413x has been internally compensated to maximize its bandwidth and slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the output decreases the device phase margin leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 37. A minimum value of 20 Ω should work well for most applications. For example, in 50-Ω transmission systems, setting the series resistor value to 50 Ω both isolates any capacitance loading and provides the proper line impedance matching at the source end.

THS4130 THS4131 ai_dcl_los318.gifFigure 37. Driving a Capacitive Load

9.1.3 Data Converters

Data converters are one of the most popular applications for the fully-differential amplifiers. Figure 38 shows a typical configuration of a fully-differential amplifier attached to a differential analog-to-digital converter (ADC).

THS4130 THS4131 ai_fdaa_adc_los318.gifFigure 38. Fully-Differential Amplifier Attached to a Differential ADC

Fully-differential amplifiers can operate with a single supply. VOCM defaults to the midrail voltage, VCC/2. The differential output may be fed into a data converter. This method eliminates the use of a transformer in the circuit. If the ADC has a reference voltage output (Vref), then it is recommended to connect it directly to the VOCM of the amplifier using a bypass capacitor for stability. For proper operation, the input common-mode voltage to the input terminal of the amplifier should not exceed the common-mode input voltage range.

THS4130 THS4131 ai_fda_ss_los318.gifFigure 39. Fully-Differential Amplifier Using a Single Supply

9.1.4 Single-Supply Applications

Some single-supply applications may require the input voltage to exceed the common-mode input voltage range. In such cases, the circuit configuration of Figure 40 is suggested to bring the common-mode input voltage within the specifications of the amplifier.

THS4130 THS4131 ai_cicmiv_los318.gifFigure 40. Circuit With Improved Common-Mode Input Voltage

Equation 9 is used to calculate RPU:

Equation 9. THS4130 THS4131 Q2_los318.gif

9.2 Typical Application

For signal conditioning in ADC applications, it is important to limit the input frequency to the ADC. Low-pass filters can prevent the aliasing of the high-frequency noise with the frequency of operation. Figure 41 presents a method by which the noise may be filtered in the THS413x.

Figure 41 shows a typical application design example for the THS413x device in active low-pass filter topology driving and ADC.

THS4130 THS4131 ai_aflt_los318.gifFigure 41. Antialias Filtering

9.2.1 Design Requirements

Table 3 shows example design parameters and values for the typical application design example in Figure 41.

Table 3. Design Parameters

DESIGN PARAMETERS VALUE
Supply voltage ±2.5 V to ±15 V
Amplifier topology Voltage feedback
Output control DC coupled with output common mode control capability
Filter requirement 500 kHz, Multiple feedback low pass filter

9.2.2 Detailed Design Procedure

9.2.2.1 Active Antialias Filtering

Figure 41 shows a multiple-feedback (MFB) lowpass filter. The transfer function for this filter circuit is:

Equation 10. THS4130 THS4131 Q3_los318.gif
Equation 11. THS4130 THS4131 Q9_los318.gif

K sets the pass band gain, fc is the cutoff frequency for the filter, FSF is a frequency scaling factor, and Q is the quality factor.

Equation 12. THS4130 THS4131 Q4_los318.gif

where Re is the real part, and Im is the imaginary part of the complex pole pair. Setting R2 = R, R3 = mR, C1 = C, and C2 = nC results in:

Equation 13. THS4130 THS4131 Q5_los318.gif

Start by determining the ratios, m and n, required for the gain and Q of the filter type being designed, then select C and calculate R for the desired fc.

9.2.3 Application Curve

THS4130 THS4131 tc_lsfr_f_los318.gifFigure 42. Large-Signal Frequency Response