SLOS318I May   2000  – August 2015 THS4130 , THS4131

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Tables
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Resistor Matching
      2. 9.1.2 Driving a Capacitive Load
      3. 9.1.3 Data Converters
      4. 9.1.4 Single-Supply Applications
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Active Antialias Filtering
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 General PowerPAD Design Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VI Input voltage –VCC +VCC V
VCC– to VCC+ Supply voltage –33 33 V
IO(2) Output current 150 mA
VID Differential input voltage –6 6 V
Continuous total power dissipation See Dissipation Ratings
TJ(3) Maximum junction temperature 150 °C
TJ(4) Maximum junction temperature, continuous operation, long-term reliability 125 °C
TA Operating free-air temperature C-suffix 0 70 °C
I-suffix –40 85 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The THS413x may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about using the PowerPAD thermally-enhanced package.
(3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
(4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device.

7.2 ESD Ratings

VALUE UNIT
THS4130: D, DGN, OR DGK PACKAGES
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(1) ±1500
THS4131: D, DGN, OR DGK PACKAGES
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Vcc+ to Vcc– Dual supply ±2.5 ±15 V
Single supply 5 30
TA C-suffix 0 70 °C
I-suffix –40 85

7.4 Thermal Information

THERMAL METRIC(1) THS413x UNIT
D (SOIC) DGN (VSSOP) DGK (HVSSOP)
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 114.5 55.8 182.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 60.3 61.6 72.3 °C/W
RθJB Junction-to-board thermal resistance 54.8 34.5 103.5 °C/W
ψJT Junction-to-top characterization parameter 14 13.8 11.6 °C/W
ψJB Junction-to-board characterization parameter 54.3 34.4 101.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics(1)

VCC= ±5 V, RL = 800Ω, and TA = +25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DYNAMIC PERFORMANCE
BW Small-signal bandwidth (–3 dB), single-ended input, differential output, VI = 63 mVPP VCC = 5 Gain = 1, Rf = 390 Ω 125 MHz
VCC = ±5 Gain = 1, Rf = 390 Ω 135
VCC = ±15 Gain = 1, Rf = 390 Ω 150
Small-signal bandwidth (–3 dB), single-ended input, differential output, VI = 63 mVPP VCC = 5 Gain = 2, Rf = 750 Ω 80
VCC = ±5 Gain = 2, Rf = 750 Ω 85
VCC = ±15 Gain = 2, Rf = 750 Ω 90
SR Slew rate(2) Gain = 1 52 V/µs
ts Settling time to 0.1% Step voltage = 2 V, gain = 1 78 ns
Settling time to 0.01% Step voltage = 2 V, gain = 1 213
DISTORTION PERFORMANCE
THD Total harmonic distortion, differential input, differential output, gain = 1, Rf = 390 Ω, RL = 800 Ω, VO= 2 VPP VCC = 5 f = 250 kHz –95 dBc
f = 1 MHz –81
VCC = ±5 f = 250 kHz –96
f = 1 MHz –80
VCC = ±15 f = 250 kHz –97
f = 1 MHz –80
VO = 4 VPP VCC = ±5 f = 250 kHz –91
f = 1 MHz –75
VCC = ±15 f = 250 kHz –91
f = 1 MHz –75
SFDR Spurious-free dynamic range, differential input, differential output, gain = 1, Rf = 390 Ω,
RL = 800 Ω, f = 250 kHz
VO= 2 VPP VCC = ±2.5 97 dB
VCC = ±5 98
VCC = ±15 99
VO = 4 VPP VCC = ±5 93
VCC = ±15 95
Third intermodulation distortion VI(PP) = 4 V, G = 1, F1 = 3 MHz, F2 = 3.5 MHz –53 dBc
Third-order intercept VI(PP) = 4 V, G = 1, F1 = 3 MHz, F2 = 3.5 MHz 41.5 dB
NOISE PERFORMANCE
Vn Input voltage noise f = 10 kHz 1.3 nV/√Hz
In Input current noise f = 10 kHz 1 pA/√Hz
DC PERFORMANCE
Open-loop gain TA = +25°C 71 78 dB
TA = full range 69
V(OS) Input offset voltage TA = +25°C 0.2 2 mV
TA = full range 3
Common-mode input offset voltage, referred to VOCM TA = +25°C 0.2 3.5
Input offset voltage drift TA = full range 4.5 µV/°C
IIB Input bias current TA = full range 2 6 µA
IOS Input offset current TA = full range 100 500 nA
Offset drift 2 nA/°C
INPUT CHARACTERISTICS
CMRR Common-mode rejection ratio TA = full range 80 95 dB
VICR Common-mode input voltage range –3.77 to 4.3 –4 to 4.5 V
RI Input resistance Measured into each input terminal 34
CI Input capacitance, closed loop 4 pF
ro Output resistance Open loop 41 Ω
OUTPUT CHARACTERISTICS
Output voltage swing VCC = 5 V TA = +25°C 1.2 to 3.8 0.9 to 4.1 V
TA = full range 1.3 to 3.7 ±4
VCC = ±5 V TA = +25°C ±3.7
TA = full range ±3.6
VCC = ±15 V TA = +25°C ±10.5 ±12.4
TA = full range ±10.2
IO Output current VCC = 5 V, RL = 7 Ω TA = +25°C 25 45 mA
TA = full range 20
VCC = ±5 V, RL = 7 Ω TA = +25°C 30 55
TA = full range 28
VCC = ±15 V, RL = 7 Ω TA = +25°C 60 85
TA = full range 65
POWER SUPPLY
VCC Supply voltage range Single supply 4 33 V
Split supply ±2 ±16.5
ICC Quiescent current VCC = ±5 V TA = +25°C 12.3 15 mA
TA = full range 16
VCC = ±15 V TA = +25°C 14
ICC(SD) Quiescent current (shutdown) (THS4130 only)(3) V = –5 V TA = +25°C 0.86 1.4 mA
TA = full range 1.5
PSRR Power-supply rejection ratio (dc) TA = +25°C 73 98 dB
TA = full range 70
(1) The full range temperature is 0°C to +70°C for the C-suffix, and –40°C to +85°C for the I-suffix.
(2) Slew rate is measured from an output level range of 25% to 75%.
(3) For detailed information on the behavior of the power-down circuit, see thePower-Down Mode section.

7.6 Dissipation Ratings

PACKAGE θJA(1) (°C/W) θJC (°C/W) POWER RATING(2)
TA= +25°C TA = +85°C
D 97.5 38.3 1.02 W 410 mW
DGN 58.4 4.7 1.71 W 685 mW
DGK 134 72 750 mW 300 mW
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and long-term reliability.

7.7 Typical Characteristics

THS4130 THS4131 tc_ssfr1_f_los318.gifFigure 1. Small-Signal Frequency Response
THS4130 THS4131 tc_ssfr_vs_f_los318.gifFigure 3. Small-Signal Frequency Response (Various Supplies)
THS4130 THS4131 tc_op_f_los318.gifFigure 5. Small-Signal Frequency Response (Various CL)
THS4130 THS4131 tc_lsfr_f_los318.gifFigure 7. Large-Signal Frequency Response
THS4130 THS4131 tc_icc_ta_los318.gifFigure 9. Supply Current vs Free-Air Temperature
THS4130 THS4131 tc_iib_ta_los318.gifFigure 11. Input Bias Current vs Free-Air Temperature
THS4130 THS4131 tc_psrr_f_los318.gifFigure 13. Power-Supply Rejection Ratio vs Frequency (Differential Out)
THS4130 THS4131 tc_thd_f_los318.gifFigure 15. Total Harmonic Distortion vs Frequency
THS4130 THS4131 tc_shd2_f_los318.gifFigure 17. Second-Harmonic Distortion vs Frequency
THS4130 THS4131 tc_shd2_vo_los318.gifFigure 19. Second-Harmonic Distortion vs Output Voltage
THS4130 THS4131 tc_thd2_f_los318.gifFigure 21. Third-Harmonic Distortion vs Frequency
THS4130 THS4131 tc_thd2_vo_los318.gifFigure 23. Third-Harmonic Distortion vs Output Voltage
THS4130 THS4131 tc_cn_f_los318.gifFigure 25. Current Noise vs Frequency
THS4130 THS4131 tc_vo_rl_los318.gifFigure 27. Output Voltage vs Differential Load Resistance
THS4130 THS4131 tc_ssfr2_f_los318.gifFigure 2. Small-Signal Frequency Response
THS4130 THS4131 tc_ssfr_vc_f_los318.gifFigure 4. Small-Signal Frequency Response (Various CF)
THS4130 THS4131 tc_lstr_t_los318.gifFigure 6. Large-Signal Transient Response (Differential In/Single Out)
THS4130 THS4131 tc_cmrr_f_los318.gifFigure 8. Common-Mode Rejection Ratio vs Frequency
THS4130 THS4131 tc_icc_tasd_los318.gifFigure 10. Supply Current vs Free-Air Temperature (Shutdown State)
THS4130 THS4131 tc_vo_t_los318.gifFigure 12. Settling Time
THS4130 THS4131 tc_lstr_tim_los318.gifFigure 14. Large-Signal Transient Response
THS4130 THS4131 tc_shd1_f_los318.gifFigure 16. Second-Harmonic Distortion vs Frequency
THS4130 THS4131 tc_shd1_vo_los318.gifFigure 18. Second-Harmonic Distortion vs Output Voltage
THS4130 THS4131 tc_thd1_f_los318.gifFigure 20. Third-Harmonic Distortion vs Frequency
THS4130 THS4131 tc_thd1_vo_los318.gifFigure 22. Third-Harmonic Distortion vs Output Voltage
THS4130 THS4131 tc_vn_f_los318.gifFigure 24. Voltage Noise vs Frequency
THS4130 THS4131 tc_iov_cmov_los318.gifFigure 26. Input Offset Voltage vs Common-Mode Output Voltage
THS4130 THS4131 tc_oi_f_los318.gifFigure 28. Output Impedance vs Frequency