SBOS877A April   2018  – September 2018 THS6301

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      MTPR G.Fast 212 MHz (Bias 10, PAR = 15 dB, 1-in-64 Missing Tones)
      2.      Multitone Power Ratio (MTPR) Profile (G.Fast, 212 MHz, 8 dBm)
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Dissipation and Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3 Feature Description

The THS6301 is a line driver that has a high current drive and a differential input and output. Figure 41 shows an example circuit of the THS6301 configured to drive the G.Fast 212-MHz DSL profile. The bias control pins B1 and B2 are set to 3.3 V and ground, respectively, to put the device in the G.Fast 212-MHz bias mode. This bias mode optimizes the internal power consumption of the device to meet performance specifications of the G.Fast 212-MHz profile and can be changed to meet several different DSL profiles and other modes listed in Table 1. The IADJ pin is biased with a 75-kΩ (RIADJ) resistor that adjusts the device quiescent current to a nominal state. RIADJ can be increased to lower the quiescent current or decreased to raise the quiescent current of the device for fine-tuning. CIADJ provides decoupling for the IADJ pin and is typically 100 pF.

The THS6301 has a 10-kΩ, internally-set differential input impedance and low output impedance. In Figure 41 the input impedance is matched to 100 Ω by using a 100-Ω resistor connected differentially across the inputs. This value can easily be changed by using a different resistor to create the desired impedance at the input. Remember that the impedance in the device is actually the parallel combination of 10 kΩ and the external input resistor. For low impedances, this effect is minimal, but must be considered if the matched input impedance is increased. The output impedance of the THS6301 in Figure 41 is set by the two RSERIES resistors to match 100 Ω. The internal output resistance is very low (< 2 Ω per output), so the output impedance is primarily set by the RSERIES resistors. These resistors can be adjusted to match various output impedance values.

THS6301 THS6301_Functional_Block_Diagram.gifFigure 41. G.Fast, 212-MHz Driving Mode Example Circuit