POWER SUPPLY |
|
|
|
IS_CONT |
Continuous mode VS power supply current |
Continuous mode, IWETT= 10 mA, all switches open, no active comparator operation, no unserviced interrupt |
|
5.6 |
7 |
mA |
IS_POLL_COMP_25 |
Polling mode VS power supply average current |
TA= 25° |
Polling mode, tPOLL= 64 ms, tPOLL_ACT= 128 µs, all switches open, IWETT= 10 mA, no unserviced interrupt |
|
68 |
100 |
µA |
IS_POLL_COMP_85 |
TA= -40° to 85°C |
|
68 |
110 |
µA |
IS_POLL_COMP |
TA= -40° to 105°C |
|
68 |
170 |
µA |
IS_RESET |
Reset mode VS power supply current |
Reset mode, VRESET= VDD. VS= 12 V, all switches open, TA=25°C |
|
12 |
17 |
µA |
IS_IDLE_25 |
VS power supply average current in idle state |
TRIGGER bit in CONFIG register = logic 0, TA= 25°C, no unserviced interrupt |
|
50 |
75 |
µA |
IS_IDLE_85 |
TRIGGER bit in CONFIG register = logic 0, TA= -40°C to 85°C, no unserviced interrupt |
|
50 |
95 |
µA |
IS_IDLE |
TRIGGER bit in CONFIG register = logic 0, TA= -40°C to 125°C, no unserviced interrupt |
|
50 |
145 |
µA |
IDD |
Logic supply current from VDD |
SCLK = SI = 0 V, CS = INT = VDD, no SPI communication |
|
1.5 |
10 |
µA |
VPOR_R |
Power on reset (POR) voltage for VS |
Threshold for rising VS from device OFF condition resulting in INT pin assertion and a flagged POR bit in the INT_STAT register |
3.85 |
|
4.5 |
V |
VPOR_F |
Threshold for falling VS from device normal operation to reset mode and loss of SPI communication |
1.95 |
|
2.8 |
V |
VOV_R |
Over-voltage (OV) condition for VS |
Threshold for rising VS from device normal operation resulting in INT pin assertion and a flagged OV bit in the INT_STAT register |
35 |
|
40 |
V |
VOV_HYST |
Over-voltage (OV) condition hysteresis for VS |
|
1 |
|
3.5 |
V |
VUV_R |
Under-voltage (UV) condition for VS |
Threshold for rising VS from under-voltage condition resulting in INT pin assertion and a flagged UV bit in the INT_STAT register |
3.85 |
|
4.5 |
V |
VUV_F |
Threshold for falling VS from under-votlage condition resulting in INT pin assertion and a flagged UV bit in the INT_STAT register |
3.7 |
|
4.4 |
V |
VUV_HYST |
Under-voltage (UV) condition hysteresis for VS(1) |
|
75 |
|
275 |
mV |
VDD_F |
|
Threshold for falling VDD resulting in loss of SPI communication |
2.5 |
|
2.9 |
V |
VDD_HYST |
Valid VDD voltage hysteresis |
|
50 |
|
150 |
mV |
WETTING CURRENT ACCURACY (DIGITAL SWITCHES, MAXIMUM RESISTANCE VALUE WITH SWITCH CLOSED ≤ 100Ω , MINIMUM RESISTANCE VALUE WITH SWITCH OPEN ≥ 5000 Ω) |
IWETT (CSO) |
Wetting current accuracy for CSO (switch closed) |
1 mA setting |
6.5 V ≤ VS ≤ 35 V |
0.84 |
1 |
1.14 |
mA |
2 mA setting |
1.71 |
2 |
2.32 |
5 mA setting |
4.3 |
5 |
5.6 |
10 mA setting |
8.4 |
10 |
11.4 |
15 mA setting |
12.5 |
15 |
17 |
IWETT (CSI) |
Wetting current accuracy for CSI (switch closed) |
1 mA setting |
0.75 |
1.1 |
2.05 |
2 mA setting |
1.6 |
2.2 |
3.3 |
5 mA setting |
4.3 |
5.6 |
7.1 |
10 mA setting |
9.2 |
11.5 |
13.4 |
15 mA setting |
13.7 |
16.5 |
19.2 |
VCSI_DROP_OPEN |
Voltage drop from INx pin to AGND across CSI (switch open) |
10 mA setting, RSW= 5kΩ |
6.5 V ≤ VS ≤ 35V |
|
|
1.7 |
V |
15 mA setting, RSW= 5kΩ |
|
|
1.7 |
VCSI_DROP_CLOSED |
Voltage drop from INx pin to ground across CSI (switch closed) |
2mA setting, IIN= 1mA |
6.5 V ≤ VS ≤ 35V |
|
|
1.2 |
V |
5mA setting, IIN= 1mA or 2mA |
|
|
1.3 |
V |
10mA setting, IIN= 1mA, 2mA, or 5mA |
|
|
1.5 |
V |
15mA setting, IIN= 1mA, 2mA, 5mA, or 10mA |
|
|
2.1 |
V |
LEAKAGE CURRENTS |
|
IIN_LEAK_OFF |
Leakage current at input INx when channel is disabled |
0 V ≤ VINx ≤ VS , channel disabled (EN_INx register bit= logic 0) |
-4 |
|
5.3 |
µA |
IIN_LEAK_OFF_25 |
0 V ≤ VINx ≤ VS , channel disabled (EN_INx register bit= logic 0), TA = 25°C |
-0.5 |
|
0.5 |
IIN_LEAK_0mA |
Leakage current at input INx when wetting current setting is 0mA |
0 V ≤ VINx ≤ 6 V, 6.5 V ≤ VS ≤ 35 V , IWETT setting = 0 mA |
-110 |
|
110 |
µA |
µA |
IIN_LEAK_LOSS_OF_GND |
Leakage current at input INx under loss of GND condition |
VS = 24 V, 0 V ≤ VINx ≤ 24 V, all grounds (AGND, DGND, and EP) = 24 V, VDD shorted to the grounds(1) |
-5 |
|
|
µA |
IIN_LEAK_LOSS_OF_VS |
Leakage current at input INx under loss of VS condition |
0 V ≤ VINx ≤ 24 V, VS shorted to the grounds = 0 V, VDD = 0 V |
|
|
5 |
µA |
LOGIC LEVELS |
|
V/INT_L |
INT output low voltage |
I/INT = 2 mA |
|
|
0.35 |
V |
I/INT = 4 mA |
|
|
0.6 |
VSO_L |
SO output low voltage |
ISO = 2 mA |
|
|
0.2VDD |
V |
VSO_H |
SO output high voltage |
ISO = -2 mA |
0.8VDD |
|
|
V |
VIN_L |
SI, SCLK, and CS input low voltage |
|
|
|
0.3VDD |
V |
VIN_H |
SI, SCLK, and CS input high voltage |
|
0.7VDD |
|
|
V |
VRESET_L |
RESET input low voltage |
|
|
|
0.8 |
V |
VRESET_H |
RESET input high voltage |
|
1.6 |
|
|
V |
RRESET_25 |
RESET pin internal pull-down resistor |
VRESET = 0 to 5.5V, TA = 25°C |
0.85 |
1.25 |
1.7 |
MΩ |
RRESET |
VRESET = 0 to 5.5V, TA = –40° to 105°C |
0.2 |
|
2.1 |
COMPARATOR PARAMETERS |
|
VTH_ COMP_2V |
Comparator threshold for 2 V |
THRES_COMP = 2 V |
1.85 |
|
2.25 |
V |
VTH_ COMP_2p7V |
Comparator threshold for 2.7 V |
THRES_COMP = 2.7 V |
2.4 |
|
2.9 |
V |
VTH_ COMP_3V |
Comparator threshold for 3 V |
THRES_COMP = 3 V |
2.85 |
|
3.3 |
V |
VTH_ COMP_4V |
Comparator threshold for 4 V |
THRES_COMP = 4 V |
3.7 |
|
4.35 |
V |
RIN, COMP |
Comparator equivalent input resistance |
THRES_COMP = 2 V |
30 |
130 |
|
kΩ |
THRES_COMP = 2.7 V |
35 |
130 |
|
THRES_COMP = 3 V |
35 |
105 |
|
THRES_COMP = 4 V |
43 |
95 |
|