SLVSCQ4 October   2014 TLC5957

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Typical Application Circuit (Multiple Daisy Chained TLC5957s)
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Pin Equivalent Input and Output Schematic Diagrams
    2. 8.2 Test Circuit
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Device Functional Modes
      1. 9.3.1  Brightness Control (BC) Function
      2. 9.3.2  Color Control (CC) Function
      3. 9.3.3  Select RIREF For a Given BC
      4. 9.3.4  Choosing BC/CC For a Different Application
        1. 9.3.4.1 Example 1: Red LED Current is 20mA, Green LED Needs 12mA, Blue LED needs 8mA
        2. 9.3.4.2 Example 2: Red LED Current is 5mA, Green LED Needs 2mA, Blue LED Needs 1mA.
      5. 9.3.5  LED Open Detection (LOD)
      6. 9.3.6  Poker Mode
      7. 9.3.7  Internal Circuit for Caterpillar Removal
      8. 9.3.8  Internal Pre-charge FET for Ghost Removal
      9. 9.3.9  Thermal Shutdown (TSD)
      10. 9.3.10 IREF Resistor Short Protection (ISP)
      11. 9.3.11 Noise Reduction
  10. 10Application and Implementation
    1. 10.1 Application Information
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Parameter Measurement Information

8.1 Pin Equivalent Input and Output Schematic Diagrams

sch_SIN_SCLK_slvscq4.gif
Figure 13. SIN, SCLK
sch_LAT_GCLK_slvscq4.gif
Figure 15. LAT, GCLK
sch_SCOUT_slvscq4.gif
Figure 14. SOUT
sch_OUTR0_OUTR15_slvscq4.gif
Figure 16. OUTR0/G0/B0 through OUTR15/G15/B15

8.2 Test Circuit

sch_rise_fall_OUTXn.gifFigure 17. Rise Time and Fall Time Test Circuit for OUTXn
sch_cons_curr_test_OUTXn.gifFigure 19. Constant Current Test Circuit for OUTXn
sch_rise_fall_SOUTn.gif
Figure 18. Rise Time and Fall Time Test Circuit for SOUT