SLOS270F Data sheet

SLOS270F March 2001 – August 2016 TLV2370 , TLV2371 , TLV2372 , TLV2373 , TLV2374 , TLV2375

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

DGS|10
- MPDS035C
N|14
- MPDI002C
D|14
- MPDS177G

Thermal pad, mechanical data (Package|Pins)

D|14
- QFND304D

Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage	Supply voltage, V_DD ⁽²⁾		16.5	V
	Differential input voltage, V_ID	–V_DD	V_DD
	Input voltage, V_I⁽²⁾	–0.2	V_DD + 0.2
Current	Input current, I_IN	–10	10	mA
Current	Output current, I_O	–100	100	mA
Temperature	Operating free-air temperature, T_A: I-suffix	–40	125	°C
	Maximum junction temperature, T_J		150
	Storage temperature, T_stg	–65	150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential voltages, are with respect to GND.

7.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted).

		MIN	MAX	UNIT
Supply voltage, V_DD	Single supply	2.7	16	V
Supply voltage, V_DD	Split supply	±1.35	±8	V
Common-mode input voltage, V_CM		0	V_DD	V
Operating free-air temperature, T_A	I-suffix	–40	125	°C
Turnon voltage (shutdown pin voltage level), V_(ON), relative to GND pin voltage			2	V
Turnoff (shutdown pin voltage level), V_(OFF), relative to GND pin voltage		0.8		V

7.3 Thermal Information: TLV2370

THERMAL METRIC⁽¹⁾		TLV2370			UNIT
		DBV (SOT-23)	D (SOIC)	P (PDIP)
		6 PINS	8 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance	228.5	138.4	49.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	99.1	89.5	39.4	°C/W
R_θJB	Junction-to-board thermal resistance	54.6	78.6	26.4	°C/W
ψ_JT	Junction-to-top characterization parameter	7.7	29.9	15.4	°C/W
ψ_JB	Junction-to-board characterization parameter	53.8	78.1	26.3	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	n/a	n/a	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information: TLV2371

THERMAL METRIC⁽¹⁾		TLV2371			UNIT
		DBV (SOT-23)	D (SOIC)	P (PDIP)
		5 PINS	8 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance	228.5	138.4	49.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	99.1	89.5	39.4	°C/W
R_θJB	Junction-to-board thermal resistance	54.6	78.6	26.4	°C/W
ψ_JT	Junction-to-top characterization parameter	7.7	29.9	15.4	°C/W
ψ_JB	Junction-to-board characterization parameter	53.8	78.1	26.3	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	n/a	n/a	°C/W

7.5 Thermal Information: TLV2372

THERMAL METRIC⁽¹⁾		TLV2372			UNIT
		D (SOIC)	DGK (VSSOP)	P (PDIP)
		8 PINS	8 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance	138.4	191.2	49.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	89.5	61.9	39.4	°C/W
R_θJB	Junction-to-board thermal resistance	78.6	111.9	26.4	°C/W
ψ_JT	Junction-to-top characterization parameter	29.9	5.1	15.4	°C/W
ψ_JB	Junction-to-board characterization parameter	78.1	110.2	26.3	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	n/a	n/a	°C/W

7.6 Thermal Information: TLV2373

THERMAL METRIC⁽¹⁾		TLV2373			UNIT
		DGS (VSSOP)	D (SOIC)	P (PDIP)
		10 PINS	14 PINS	14 PINS
R_θJA	Junction-to-ambient thermal resistance	166.5	67	66.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	41.8	24.1	20.5	°C/W
R_θJB	Junction-to-board thermal resistance	86.1	22.5	26.8	°C/W
ψ_JT	Junction-to-top characterization parameter	1.5	2.2	2.1	°C/W
ψ_JB	Junction-to-board characterization parameter	84.7	22.1	26.2	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	n/a	n/a	°C/W

7.7 Thermal Information: TLV2374

THERMAL METRIC⁽¹⁾		TLV2374			UNIT
		D (SOIC)	N (PDIP)	PW (TSSOP)
		14 PINS	14 PINS	14 PINS
R_θJA	Junction-to-ambient thermal resistance	67	66.3	121	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	24.1	20.5	49.4	°C/W
R_θJB	Junction-to-board thermal resistance	22.5	26.8	62.8	°C/W
ψ_JT	Junction-to-top characterization parameter	2.2	2.1	5.9	°C/W
ψ_JB	Junction-to-board characterization parameter	22.1	26.2	62.2	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	n/a	n/a	°C/W

7.8 Thermal Information: TLV2375

THERMAL METRIC⁽¹⁾		TLV2375			UNIT
		D (SOIC)	N (PDIP)	PW (TSSOP)
		16 PINS	16 PINS	16 PINS
R_θJA	Junction-to-ambient thermal resistance	83	55.8	115.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	44	43.1	50.5	°C/W
R_θJB	Junction-to-board thermal resistance	40.5	35.8	60.7	°C/W
ψ_JT	Junction-to-top characterization parameter	11.5	27.9	7.4	°C/W
ψ_JB	Junction-to-board characterization parameter	40.2	35.7	60.1	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	n/a	n/a	°C/W

7.9 Electrical Characteristics

at T_A = 25°C, V_DD = 2.7 V, 5 V, and 15 V (unless otherwise noted).

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
DC PERFORMANCE
V_OS	Input offset voltage	At T_A = 25°C, V_IC = V_DD/2, V_O = V_DD/2, R_S = 50 Ω			2	4.5	mV
V_OS	Input offset voltage	At T_A = –40°C to +125°C, V_IC = V_DD/2, V_O = V_DD/2, R_S = 50 Ω				6	mV
dV_OS/dT	Offset voltage drift	At T_A = 25°C, V_IC = V_DD/2, V_O = V_DD/2, R_S = 50 Ω			2		µV/°C
CMRR	Common-mode rejection ratio	V_DD= 2.7 V, R_S = 50 Ω	V_IC = 0 to V_DD	50	68		dB
			At T_A = –40°C to +125°C, V_IC = 0 to V_DD	49
			V_IC = 0 to V_DD − 1.35 V	56	70
			At T_A = –40°C to +125°C, V_IC = 0 to V_DD − 1.35 V	54
		V_DD= 5 V, R_S = 50 Ω	V_IC = 0 to V_DD	55	72
			At T_A = –40°C to +125°C, V_IC = 0 to V_DD	54
			V_IC = 0 to V_DD − 1.35 V	67	80
			At T_A = –40°C to +125°C, V_IC = 0 to V_DD − 1.35 V	64
		V_DD= 15 V, R_S = 50 Ω	V_IC = 0 to V_DD	64	82
			At T_A = –40°C to +125°C, V_IC = 0 to V_DD	63
			V_IC = 0 to V_DD − 1.35 V	67	84
			At T_A = –40°C to +125°C, V_IC = 0 to V_DD − 1.35 V	66
A_VD	Large-signal differential voltage amplification	V_DD= 2.7 V, V_O(PP) = V_DD/2, R_L = 10 kΩ		98	106		dB
		V_DD= 2.7 V, V_O(PP) = V_DD/2, R_L = 10 kΩ	At T_A = –40°C to +125°C	76
		V_DD= 5 V, V_O(PP) = V_DD/2, R_L = 10 kΩ		100	110
		V_DD= 5 V, V_O(PP) = V_DD/2, R_L = 10 kΩ	At T_A = –40°C to +125°C	86
		V_DD= 15 V, V_O(PP) = V_DD/2, R_L = 10 kΩ		81	83
		V_DD= 15 V, V_O(PP) = V_DD/2, R_L = 10 kΩ	At T_A = –40°C to +125°C	79
INPUT CHARACTERISTICS
I_OS	Input offset current	V_DD = 15 V, V_IC = V_O = V_DD/2			1	60	pA
			At T_A = 70°C			100
			At T_A = 125°C			1000
I_B	Input bias current	V_DD = 15 V, V_IC = V_O = V_DD/2			1	60	pA
			At T_A = 70°C			100
			At T_A = 125°C			1000
	Differential input resistance				1000		GΩ
	Common-mode input capacitance	f = 21 kHz			8		pF
OUTPUT CHARACTERISTICS
V_OH	High-level output voltage	V_DD= 2.7 V	At T_A = 25°C, V_IC = V_DD/2, I_OH = −1 mA	2.55	2.58		V
		V_DD= 2.7 V	At T_A = –40°C to +125°C, V_IC = V_DD/2, I_OH = −1 mA	2.48
		V_DD= 5 V	At T_A = 25°C, V_IC = V_DD/2, I_OH = −1 mA	4.9	4.93
		V_DD= 5 V	At T_A = –40°C to +125°C, V_IC = V_DD/2, I_OH = −1 mA	4.85
		V_DD= 15 V	At T_A = 25°C, V_IC = V_DD/2, I_OH = −1 mA	14.92	14.96
		V_DD= 15 V	At T_A = –40°C to +125°C, V_IC = V_DD/2, I_OH = −1 mA	14.9
		V_DD= 2.7 V	At T_A = 25°C, V_IC = V_DD/2, I_OH = −5 mA	1.9	2
		V_DD= 2.7 V	At T_A = –40°C to +125°C, V_IC = V_DD/2, I_OH = −5 mA	1.6
		V_DD= 5 V	At T_A = 25°C, V_IC = V_DD/2, I_OH = −5 mA	4.6	4.68
		V_DD= 5 V	At T_A = –40°C to +125°C, V_IC = V_DD/2, I_OH = −5 mA	4.5
		V_DD= 15 V	At T_A = 25°C, V_IC = V_DD/2, I_OH = −5 mA	14.7	14.8
		V_DD= 15 V	At T_A = –40°C to +125°C, V_IC = V_DD/2, I_OH = −5 mA	14.6
V_OL	Low-level output voltage	V_DD= 2.7 V	At T_A = 25°C, V_IC = V_DD/2, I_OL = 1 mA		0.1	0.15
		V_DD= 2.7 V	At T_A = –40°C to +125°C, V_IC = V_DD/2, I_OL = 1 mA			0.22	V
		V_DD= 5 V	At T_A = 25°C, V_IC = V_DD/2, I_OL = 1 mA		0.05	0.1
		V_DD= 5 V	At T_A = –40°C to +125°C, V_IC = V_DD/2, I_OL = 1 mA			0.15
		V_DD= 15 V	At T_A = 25°C, V_IC = V_DD/2, I_OL = 1 mA		0.05	0.08
		V_DD= 15 V	At T_A = –40°C to +125°C, V_IC = V_DD/2, I_OL = 1 mA			0.1
		V_DD= 2.7 V	At T_A = 25°C, V_IC= V_DD/2, I_OL = 5 mA		0.52	0.7
		V_DD= 2.7 V	At T_A = –40°C to +125°C, V_IC= V_DD/2, I_OL = 5 mA			1.1
		V_DD= 5 V	At T_A = 25°C, V_IC= V_DD/2, I_OL = 5 mA		0.28	0.4
		V_DD= 5 V	At T_A = –40°C to +125°C, V_IC= V_DD/2, I_OL = 5 mA			0.5
		V_DD= 15 V	At T_A = 25°C, V_IC= V_DD/2, I_OL = 5 mA		0.19	0.3
		V_DD= 15 V	At T_A = –40°C to +125°C, V_IC= V_DD/2, I_OL = 5 mA			0.35
I_O	Output current	V_DD= 2.7 V, V_O = 0.5 V from rail	Positive rail		4		mA
		V_DD= 2.7 V, V_O = 0.5 V from rail	Negative rail		5
		V_DD= 5 V, V_O = 0.5 V from rail	Positive rail		7
		V_DD= 5 V, V_O = 0.5 V from rail	Negative rail		8
		V_DD= 15 V, V_O = 0.5 V from rail	Positive rail		16
		V_DD= 15 V, V_O = 0.5 V from rail	Negative rail		15
POWER SUPPLY
I_DD	Supply current (per channel)	V_DD= 2.7 V, V_O = V_DD/2			470	560	µA
		V_DD= 5 V, V_O = V_DD/2			550	660
		V_DD= 15 V, V_O = V_DD/2	At T_A = 25°C		750	900
		V_DD= 15 V, V_O = V_DD/2	At T_A = –40°C to +125°C			1200
PSRR	Power-supply rejection ratio (ΔV_DD/ΔV_IO)	V_DD = 2.7 V to 15 V, V_IC = V_DD/2, no load	At T_A = 25°C	70	80		dB
PSRR	Power-supply rejection ratio (ΔV_DD/ΔV_IO)	V_DD = 2.7 V to 15 V, V_IC = V_DD/2, no load	At T_A = –40°C to +125°C	65			dB
DYNAMIC PERFORMANCE
UGBW	Unity gain bandwidth	V_DD= 2.7 V	R_L= 2 kΩ, C_L= 10 pF		2.4		MHz
UGBW	Unity gain bandwidth	V_DD= 5 V to 15 V	R_L= 2 kΩ, C_L= 10 pF		3		MHz
SR	Slew rate at unity gain	V_DD= 2.7 V	At T_A = 25°C, V_O(PP) = V_DD/2, C_L= 50 pF, R_L = 10 kΩ	1.4	2		V/µs
		V_DD= 2.7 V	At T_A = –40°C to +125°C, V_O(PP) = V_DD/2, C_L= 50 pF, R_L = 10 kΩ	1
		V_DD= 5 V	At T_A = 25°C, V_O(PP) = V_DD/2, C_L= 50 pF, R_L = 10 kΩ	1.6	2.4
		V_DD= 5 V	At T_A = –40°C to +125°C, V_O(PP) = V_DD/2, C_L= 50 pF, R_L = 10 kΩ	1.2
		V_DD= 15 V	At T_A = 25°C, V_O(PP) = V_DD/2, C_L= 50 pF, R_L = 10 kΩ	1.9	2.1
		V_DD= 15 V	At T_A = –40°C to +125°C, V_O(PP) = V_DD/2, C_L= 50 pF, R_L = 10 kΩ	1.4
φm	Phase margin	R_L= 2 kΩ, C_L= 100 pF			65		°
	Gain margin	R_L= 2 kΩ, C_L= 10 pF			18		dB
t_s	Settling time	V_DD = 2.7 V, V_(STEP)PP = 1 V, A_V = −1, C_L = 10 pF, R_L = 2 kΩ, 0.1%			2.9		µs
t_s	Settling time	V_DD = 5 V, 15 V, V_(STEP)PP = 1 V, A_V = −1, C_L = 47 pF, R_L = 2 kΩ, 0.1%			2		µs
NOISE, DISTORTION PERFORMANCE
THD + N	Total harmonic distortion plus noise	V_DD = 2.7 V	V_O(PP)= V_DD/2 V, R_L = 2 kΩ, f = 10 kHz, A_V = 1		0.02%
			V_O(PP)= V_DD/2 V, R_L = 2 kΩ, f = 10 kHz, A_V = 10		0.05%
			V_O(PP)= V_DD/2 V, R_L = 2 kΩ, f = 10 kHz, A_V = 100		0.18%
		V_DD = 5 V, 15 V	V_O(PP)= V_DD/2 V, R_L = 2 kΩ, f = 10 kHz, A_V = 1		0.02%
			V_O(PP)= V_DD/2 V, R_L = 2 kΩ, f = 10 kHz, A_V = 10		0.09%
			V_O(PP)= V_DD/2 V, R_L = 2 kΩ, f = 10 kHz, A_V = 100		0.5%
V_n	Equivalent input noise voltage	f = 1 kHz			39		nV/√Hz
V_n	Equivalent input noise voltage	f = 10 kHz			35		nV/√Hz
I_n	Equivalent input noise current	f = 1 kHz			0.6		fA/√Hz
SHUTDOWN CHARACTERISTICS
I_DD(SHDN)	Supply current in shutdown mode (TLV2370, TLV2373, TLV2375) (per channel)	V_DD = 2.7 V, 5 V, SHDN = 0 V	At T_A = 25°C		25	30	µA
		V_DD = 2.7 V, 5 V, SHDN = 0 V	At T_A = –40°C to +125°C			35
		V_DD = 15 V, SHDN = 0 V	At T_A = 25°C		40	45
		V_DD = 15 V, SHDN = 0 V	At T_A = –40°C to +125°C			50
t_(on)	Amplifier turnon time⁽¹⁾	R_L= 2 kΩ			0.8		µs
t_(off)	Amplifier turnoff time⁽¹⁾	R_L= 2 kΩ			1		µs

(1) Disable time and enable time are defined as the interval between application of the logic signal to the SHDN terminal and the point at which the supply current has reached one half of its final value.

7.10 Typical Characteristics

Table 3. Table of Graphs

			FIGURE
V_IO	Input offset voltage	vs Common-mode input voltage	Figure 2, Figure 3, Figure 4
CMRR	Common-mode rejection ratio	vs Frequency	Figure 5
	Input bias and offset current	vs Free-air temperature	Figure 6
V_OL	Low-level output voltage	vs Low-level output current	Figure 7, Figure 9, Figure 11
V_OH	High-level output voltage	vs High-level output current	Figure 8, Figure 10, Figure 12
V_O(PP)	Peak-to-peak output voltage	vs Frequency	Figure 13
I_DD	Supply current	vs Supply voltage	Figure 14
PSRR	Power supply rejection ratio	vs Frequency	Figure 15
A_VD	Differential voltage gain and phase	vs Frequency	Figure 16
	Gain-bandwidth product	vs Free-air temperature	Figure 17
SR	Slew rate	vs Supply voltage	Figure 18
SR	Slew rate	vs Free-air temperature	Figure 19
φm	Phase margin	vs Capacitive load	Figure 20
V_n	Equivalent input noise voltage	vs Frequency	Figure 21
	Voltage-follower large-signal pulse response		Figure 22, Figure 23
	Voltage-follower small-signal pulse response		Figure 24
	Inverting large-signal response		Figure 25, Figure 26
	Inverting small-signal response		Figure 27
	Crosstalk	vs Frequency	Figure 28
	Shutdown forward & reverse isolation	vs Frequency	Figure 29
I_DD(SHDN)	Shutdown supply current	vs Supply voltage	Figure 30
I_DD(SHDN)	Shutdown pin leakage current	vs Shutdown pin voltage	Figure 31
I_DD(SHDN)	Shutdown supply current, output voltage	vs Time	Figure 32, Figure 33