SLAS666B January 2010 – October 2018 TLV320DAC3101
PRODUCTION DATA.
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | 0000 0000: Page 0 selected
0000 0001: Page 1 selected ... 1111 1110: Page 254 selected 1111 1111: Page 255 selected |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | XXXX XXXX | Reserved. Do not write to these registers. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: HPL output driver is powered down.
1: HPL output driver is powered up. |
D6 | R/W | 0 | 0: HPR output driver is powered down.
1: HPR output driver is powered up. |
D5 | R/W | 0 | Reserved. Write only zero to this bit. |
D4–D3 | R/W | 0 | 00: Output common-mode voltage = 1.35 V
01: Output common-mode voltage = 1.5 V 10: Output common-mode voltage = 1.65 V 11: Output common-mode voltage = 1.8 V |
D2 | R/W | 1 | Reserved. Write only 1 to this bit. |
D1 | R/W | 0 | 0: If short-circuit protection is enabled for headphone driver and short circuit detected, device limits the
maximum current to the load. 1: If short-circuit protection is enabled for headphone driver and short circuit detected, device powers down the output driver. |
D0 | R | 0 | 0: Short circuit is not detected on the headphone driver.
1: Short circuit is detected on the headphone driver. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: Left-channel class-D output driver is powered down.
1: Left-channel class-D output driver is powered up. |
D6 | R/W | 0 | 0: Right-channel class-D output driver is powered down.
1: Right-channel class-D output driver is powered up. |
D5–D1 | R/W | 00 011 | Reserved. Write only the reset value to this bit. |
D0 | R | 0 | 0: Short circuit is not detected on the class-D driver. Valid only if class-D amplifier is powered up. For
short-circuit flag sticky bit, see page 0 / register 44. 1: Short circuit is detected on the class-D driver. Valid only if class-D amp is powered-up. For short- circuit flag sticky bit, see page 0 / register 44. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | Reserved. Write only the reset value to this bit. |
D6–D4 | R/W | 000 | Speaker power-up wait time (duration based on using internal oscillator)
000: Wait time = 0 ms 001: Wait time = 3.04 ms 010: Wait time = 7.62 ms 011: Wait time = 12.2 ms 100: Wait time = 15.3 ms 101: Wait time = 19.8 ms 110: Wait time = 24.4 ms 111: Wait time = 30.5 ms Note: These values are based on typical oscillator frequency of 8.2 MHz. Scale according to the actual oscillator frequency. |
D3–D0 | R/W | 0000 | Reserved. Write only the reset value to these bits. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D6 | R/W | 00 | 00: DAC_L is not routed anywhere.
01: DAC_L is routed to the left-channel mixer amplifier. 10: DAC_L is routed directly to the HPL driver. 11: Reserved |
D5 | R/W | 0 | 0: AIN1 input is not routed to the left-channel mixer amplifier.
1: AIN1 input is routed to the left-channel mixer amplifier. |
D4 | 0 | 0: AIN2 input is not routed to the left-channel mixer amplifier.
1: AIN2 input is routed to the left-channel mixer amplifier. |
|
D3–D2 | R/W | 00 | 00: DAC_R is not routed anywhere.
01: DAC_R is routed to the right-channel mixer amplifier. 10: DAC_R is routed directly to the HPR driver. 11: Reserved |
D1 | R/W | 0 | 0: AIN2 input is not routed to the right-channel mixer amplifier.
1: AIN2 input is routed to the right-channel mixer amplifier. |
D0 | R/W | 0 | 0: HPL driver output is not routed to the HPR driver.
1: HPL driver output is routed to the HPR driver input (used for differential output mode). |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: Left-channel analog volume control is not routed to HPL output driver.
1: Left-channel analog volume control is routed to HPL output driver. |
D6–D0 | R/W | 111 1111 | Left-channel analog volume control gain (non-linear) for the HPL output driver, 0 dB to –78 dB. See Table 6-24. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: Right-channel analog volume control output is not routed to HPR output driver.
1: Right-channel analog volume control is routed to HPR output driver. |
D6–D0 | R/W | 111 1111 | Right-channel analog volume control gain (non-linear) for the HPR output driver, 0 dB to –78 dB. See Table 6-24. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: Left-channel analog volume control output is not routed to left-channel class-D output driver.
1: Left-channelanalog volume control output is routed to left-channel class-D output driver. |
D6–D0 | R/W | 111 1111 | Left-channelanalog volume control output gain (non-linear) for the left-channel class-D output driver, 0 dB to –78 dB. See Table 6-24. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: Right-channel analog volume control output is not routed to right-channel class-D output driver.
1: Right-channel analog volume control output is routed to right-channel class-D output driver. |
D6–D0 | R/W | 111 1111 | Right-channel analog volume control output gain (non-linear) for the right-channel class-D output driver, 0 dB to –78 dB. See and Table 6-24. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D5 | R/W | 000 | Reserved. Write only zeros to these bits. |
D4–D3 | R/W | 00 | 00: Left-channel class-D driver output stage gain = 6 dB
01: Left-channel class-D driver output stage gain = 12 dB 10: Left-channel class-D driver output stage gain = 18 dB 11: Left-channel class-D driver output stage gain = 24 dB |
D2 | R/W | 0 | 0: Left-channel class-D driver is muted.
1: Left-channel class-D driver is not muted. |
D1 | R/W | 0 | Reserved. Write only zero to this bit. |
D0 | R | 0 | 0: Not all programmed gains to the Left-channel class-D driver have been applied yet.
1: All programmed gains to the Left-channel class-D driver have been applied. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D5 | R/W | 000 | Reserved. Write only zeros to these bits. |
D4–D3 | R/W | 00 | 00: Right-channel class-D driver output stage gain = 6 dB
01: Right-channel class-D driver output stage gain = 12 dB 10: Right-channel class-D driver output stage gain = 18 dB 11: Right-channel class-D driver output stage gain = 24 dB |
D2 | R/W | 0 | 0: Right-channel class-D driver is muted.
1: Right-channel class-D driver is not muted. |
D1 | R/W | 0 | Reserved. Write only zero to this bit. |
D0 | R | 0 | 0: Not all programmed gains to right-channel class-D driver have been applied yet.
1: All programmed gains to right-channel class-D driver have been applied. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION | ||
---|---|---|---|---|---|
D7–D5 | R/W | 000 | Debounce time for the headset short-circuit detection | ||
(1) | MCLK/DIV (Page 3 / register 16) = 1-MHz Source | Internal Oscillator Source | |||
000: Debounce time =
001: Debounce time = 010: Debounce time = 011: Debounce time = 100: Debounce time = 101: Debounce time = 110: Debounce time = 111: Debounce time = |
0 μs
8 μs 16 μs 32 μs 64 μs 128 μs 256 μs 512 μs |
0 μs
7.8 μs 15.6 μs 31.2 μs 62.4 μs 124.9 μs 250 μs 500 μs Note: These values are based on a nominal oscillator frequency of 8.2 MHz. The values scale to the actual oscillator frequency. |
|||
D4–D3 | R/W | 00 | 00: Default mode for the DAC
01: DAC performance increased by increasing the current 10: Reserved 11: DAC performance increased further by increasing the current again |
||
D2 | R/W | 0 | 0: HPL output driver is programmed as headphone driver.
1: HPL output driver is programmed as lineout driver. |
||
D1 | R/W | 0 | 0: HPR output driver is programmed as headphone driver.
1: HPR output driver is programmed as lineout driver. |
||
D0 | R/W | 0 | Reserved. Write only zero to this bit. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | XXXX XXXX | Reserved. Do not write to these registers. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: Device software power down is not enabled.
1: Device software power down is enabled. |
D6–D4 | R/W | 000 | Reserved. Write only zeros to these bits. |
D3 | R/W | 0 | 0: Programmed MICBIAS is not powered up if headset detection is enabled but headset is not inserted.
1: Programmed MICBIAS is powered up even if headset is not inserted. |
D2 | R/W | 0 | Reserved. Write only zero to this bit. |
D1–D0 | R/W | 00 | 00: MICBIAS output is powered down.
01: MICBIAS output is powered to 2 V. 10: MICBIAS output is powered to 2.5 V. 11: MICBIAS output is powered to AVDD. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: AIN1 input is floating, if it is not used for the analog bypass.
1: AIN1 input is connected to CM internally, if it is not used for the analog bypass. |
D6 | R/W | 0 | 0: AIN2 input is floating, if it is not used for the analog bypass.
1: AIN2 input is connected to CM internally, if it is not used for the analog bypass. |
D5–D0 | R/W | 00 0000 | Reserved. Write only zeros to these bits. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | XXXX XXXX | Reserved. Write only the reset value to these bits. |