SLAS666B January 2010 – October 2018 TLV320DAC3101
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INTERNAL OSCILLATOR—RC_CLK | ||||||
Oscillator frequency | 8.2 | MHz | ||||
VOLUME CONTROL PIN (ADC); VOL/MICDET pin enabled | ||||||
Input voltage range | VOL/MICDET pin configured as volume control (page 0 / register 116, bit D7 = 1 and page 0 / register 67, bit D7 = 0) | 0 | 0.5 x AVDD | V | ||
Input capacitance | 2 | pF | ||||
Volume control steps | 128 | Steps | ||||
MICROPHONE BIAS | ||||||
Voltage output | Page 1 / register 46, bits D1–D0 = 10 | 2.25 | 2.5 | 2.75 | V | |
Page 1 / register 46, bits D1–D0 = 01 | 2 | |||||
Voltage regulation | At 4-mA load current, page 1 / register 46, bits D1–D0 = 10 (MICBIAS = 2.5 V) | 5 | mV | |||
At 4-mA load current, page 1 / register 46, bits D1–D0 = 01 (MICBIAS = 2 V) | 7 | |||||
DAC HEADPHONE OUTPUT, AC-coupled load = 16 Ω (single-ended), driver gain = 0 dB, parasitic capacitance = 30 pF | ||||||
Full-scale output voltage (0 dB) | Output common-mode setting = 1.65 V | 0.707 | VRMS | |||
SNR | Signal-to-noise ratio | Measured as idle-channel noise, A-weighted(1)(2) | 80 | 95 | dB | |
THD | Total harmonic distortion | 0-dBFS input | –85 | –65 | dB | |
THD+N | Total harmonic distortion + noise | 0-dBFS input | –82 | –60 | dB | |
Mute attenuation | 87 | dB | ||||
PSRR | Power-supply rejection ratio(4) | Ripple on HPVDD (3.3 V) = 200 mVp-p at 1 kHz | –62 | dB | ||
PO | Maximum output power | RL = 32 Ω, THD+N = –60 dB | 20 | mW | ||
RL = 16 Ω, THD+N = –60 dB | 60 | |||||
DAC LINEOUT (HP Driver in Lineout Mode) | ||||||
SNR | Signal-to-noise ratio | Measured as idle-channel noise, A-weighted | 95 | dB | ||
THD | Total harmonic distortion | 0-dBFS input, 0-dB gain | –86 | dB | ||
THD+N | Total harmonic distortion + noise | 0-dBFS input, 0-dB gain | –82 | dB | ||
DAC Digital Interpolation Filter Characteristics | ||||||
See Section 6.3.10.1.4 for DAC interpolation filter characteristics. | ||||||
DAC Output to Class-D Speaker Output; Load = 8 Ω (Differential), 50 pF | ||||||
Output voltage | SPLVDD = SPRVDD = 3.6 V, BTL measurement, CM = 1.8 V, DAC input = 0 dBFS, class-D gain = 6 dB, THD = –16.5 dB | 2.2 | VRMS | |||
SPLVDD = SPRVDD = 3.6 V, BTL measurement, CM = 1.8 V, DAC input = –2 dBFS, class-D gain = 6 dB, THD = –20 dB | 2.1 | |||||
Output, common-mode | SPLVDD = SPRVDD = 3.6 V, BTL measurement, DAC input = mute, CM = 1.8 V, class-D gain = 6 dB | 1.8 | V | |||
SNR | Signal-to-noise ratio | SPLVDD = SPRVDD = 3.6 V, BTL measurement, class-D gain = 6 dB, measured as idle-channel noise, A-weighted (with respect to full-scale output value of 2.2 VRMS)(1)(2) | 87 | dB | ||
THD | Total harmonic distortion | SPLVDD = SPRVDD = 3.6 V, BTL measurement, CM = 1.8 V, class-D gain = 6 dB | –67 | dB | ||
THD+N | Total harmonic distortion + noise | SPLVDD = SPRVDD = 3.6 V, BTL measurement, CM = 1.8 V, class-D gain = 6 dB | –66 | dB | ||
PSRR | Power-supply rejection ratio(3) | SPLVDD = SPRVDD = 3.6 V, BTL measurement, ripple on SPLVDD/SPRVDD = 200 mVp-p at 1 kHz | –44 | dB | ||
Mute attenuation | 110 | dB | ||||
PO | Maximum output power | SPLVDD = SPRVDD = 3.6 V, BTL measurement, CM = 1.8 V, class-D gain = 18 dB, THD = 10% | 540 | mW | ||
SPLVDD = SPRVDD = 4.3 V, BTL measurement, CM = 1.8 V, class-D gain = 18 dB, THD = 10% | 790 | mW | ||||
SPLVDD = SPRVDD = 5.5 V, BTL measurement, CM = 1.8 V, class-D gain = 18 dB, THD = 10% | 1.29 | W | ||||
Output-stage leakage current SPLVDD = SPRVDD = 4.3 V, device is powered for direct battery connection | SPLVDD = SPRVDD = 4.3 V, device is powered down (power-up-reset condition) | 80 | nA | |||
DAC Power Consumption | ||||||
For DAC power consumption based on the selected processing block, see Section 6.3.8. | ||||||
DIGITAL INPUT/OUTPUT | ||||||
Logic family | CMOS | |||||
VIH | Logic Level | IIH = 5 µA, IOVDD ≥ 1.6 V | 0.7 × IOVDD | V | ||
IIH = 5 µA, IOVDD < 1.6 V | IOVDD | |||||
VIL | IIL = 5 µA, IOVDD ≥ 1.6 V | –0.3 | 0.3 × IOVDD | |||
IIL = 5 µA, IOVDD < 1.6 V | 0 | |||||
VOH | IOH = 2 TTL loads | 0.8 × IOVDD | ||||
VOL | IOL = 2 TTL loads | 0.1 × IOVDD | ||||
Capacitive load | 10 | pF |