2 Revision History
Changes from A Revision (May 2012) to B Revision
- Added Device Information table, ESD Ratings table, Feature Description section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go
- Added Power-Supply Sequence section to the Device Initialization sectionGo
- Changed Section 6.3.10.1.2 diagrams for PRB_P2/5/8/10/13/15/18/21/24/25 to reflect that the DRC_HPF filter cannot be bypassed when the DRC is turned off Go
- Added sequence for inserting a beep in the middle of an already-playing signal and note text following script in the Key-Click Functionality With Digital Sine-Wave Generator (PRB_P25) sectionGo
- Changed PRB_Rx to PRB_Px in DAC Setup sectionGo
- Changed text from: "the rising edge of the word clock..." To: "the rising edge of the word clock..." in the DSP ModeGo
- Changed DOSR note in Page 0 / Register 14 by switching multiple value for Filter Type A and Filter Type CGo
- Changed description in Page 0 / Register 14 to remove parameters for miniDSPGo
- Changed reset value to include all bits instead of just two (xx)Go
- Deleted reference to Dig_Mic_In in Page 0 / Register 54 table for bits D2-D1Go
- Changed values in Page 0 / Register 69 (0x45): DRC Control 2Go
- Changed Page 0, Register 70, bit D3-D0 decay rate value for 0000 from DR = 1.5625e–3 to DR = 0.015625Go
- Switched D1 and D0 descriptions so that D1 is for SP and D0 is for HP in Page 1 / Register 30 tableGo
- Changed Page 1 / Register 40, D1 to reservedGo
- Changed Page 1 / Register 41, D1 to reservedGo
- Added Figure 9-1Go
Changes from * Revision (January, 2010) to A Revision
- Changed register 36 to register 35.Go
- Added D6–D0 to the Register Value column heading and changed Analog Attenuation to Analog Gain.Go
- Deleted Analog Volume Control for Headphone and Speaker Outputs (for D7=0) table and added table note to D7=1 table.Go
- Changed page 0 to page 1 in section 5.5.12.1.Go
- Added 80 MHz ≤ (PLL_CLKIN × J.D × R/P) ≤ 110 MHz and 4 ≤ R × J ≤ 259 underneath Equation 8Go
- Added Timer section and image after PLL section.Go
- Added table note to Page 0 / Register 64 (0x40): DAC VOLUME CONTROL.Go
- Changed D0=1 to Reserved in Page 1 / Register 33.Go
- Removed extraneous cross-references for deleted table.Go
- Added table note following Page 1 / Register 40Go
- Added table note to Page 1 / Register 41 (0x29): HPR Driver.Go