SLAS666B January   2010  – October 2018 TLV320DAC3101

PRODUCTION DATA.  

  1. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Attributes
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics
    6. 4.6  Power Dissipation Ratings
    7. 4.7  I2S, LJF, and RJF Timing in Slave Mode
    8. 4.8  DSP Timing in Master Mode
    9. 4.9  DSP Timing in Slave Mode
    10. 4.10 I2C Interface Timing
    11. 4.11 Typical Characteristics
      1. 4.11.1 DAC Performance
      2. 4.11.2 Class-D Speaker Driver Performance
      3. 4.11.3 Analog Bypass Performance H
      4. 4.11.4 MICBIAS Performance H
  5. 5Parameter Measurement Information
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Supply Sequence
      2. 6.3.2  Reset
      3. 6.3.3  Device Start-Up Lockout Times
      4. 6.3.4  PLL Start-Up
      5. 6.3.5  Power-Stage Reset
      6. 6.3.6  Software Power Down
      7. 6.3.7  Audio Analog I/O
      8. 6.3.8  Digital Processing Low-Power Modes
        1. 6.3.8.1 DAC Playback on Headphones, Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
        2. 6.3.8.2 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
        3. 6.3.8.3 DAC Playback on Headphones, Stereo, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
        4. 6.3.8.4 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
        5. 6.3.8.5 DAC Playback on Headphones, Stereo, 192 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
        6. 6.3.8.6 DAC Playback on Line Out (10 k-Ω load), Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3 V, HPVDD = 3 V
      9. 6.3.9  Analog Signals
        1. 6.3.9.1 MICBIAS
        2. 6.3.9.2 Analog Inputs AIN1 and AIN2
      10. 6.3.10 Audio DAC and Audio Analog Outputs
        1. 6.3.10.1  DAC
          1. 6.3.10.1.1 DAC Processing Blocks
          2. 6.3.10.1.2 DAC Processing Blocks — Details
            1. 6.3.10.1.2.1  Three Biquads, Filter A
            2. 6.3.10.1.2.2  Six Biquads, First-Order IIR, DRC, Filter A or B
            3. 6.3.10.1.2.3  Six Biquads, First-Order IIR, Filter A or B
            4. 6.3.10.1.2.4  IIR, Filter B or C
            5. 6.3.10.1.2.5  Four Biquads, DRC, Filter B
            6. 6.3.10.1.2.6  Four Biquads, Filter B
            7. 6.3.10.1.2.7  Four Biquads, First-Order IIR, DRC, Filter C
            8. 6.3.10.1.2.8  Four Biquads, First-Order IIR, Filter C
            9. 6.3.10.1.2.9  Two Biquads, 3D, Filter A
            10. 6.3.10.1.2.10 Five Biquads, DRC, 3D, Filter A
            11. 6.3.10.1.2.11 Five Biquads, DRC, 3D, Beep Generator, Filter A
          3. 6.3.10.1.3 DAC User-Programmable Filters
            1. 6.3.10.1.3.1 First-Order IIR Section
            2. 6.3.10.1.3.2 Biquad Section
          4. 6.3.10.1.4 DAC Interpolation Filter Characteristics
            1. 6.3.10.1.4.1 Interpolation Filter A
            2. 6.3.10.1.4.2 Interpolation Filter B
            3. 6.3.10.1.4.3 Interpolation Filter C
        2. 6.3.10.2  DAC Digital-Volume Control
        3. 6.3.10.3  Volume Control Pin
        4. 6.3.10.4  Dynamic Range Compression
          1. 6.3.10.4.1 DRC Threshold
          2. 6.3.10.4.2 DRC Hysteresis
          3. 6.3.10.4.3 DRC Hold Time
          4. 6.3.10.4.4 DRC Attack Rate
          5. 6.3.10.4.5 DRC Decay Rate
          6. 6.3.10.4.6 Example Setup for DRC
        5. 6.3.10.5  Headphone Detection
        6. 6.3.10.6  Interrupts
        7. 6.3.10.7  Key-Click Functionality With Digital Sine-Wave Generator (PRB_P25)
        8. 6.3.10.8  Programming DAC Digital Filter Coefficients
        9. 6.3.10.9  Updating DAC Digital Filter Coefficients During PLAY
        10. 6.3.10.10 Digital Mixing and Routing
        11. 6.3.10.11 Analog Audio Routing
          1. 6.3.10.11.1 Analog Output Volume Control
          2. 6.3.10.11.2 Headphone Analog-Output Volume Control
          3. 6.3.10.11.3 Class-D Speaker Analog Output Volume Control
        12. 6.3.10.12 Analog Outputs
          1. 6.3.10.12.1 Headphone Drivers
          2. 6.3.10.12.2 Speaker Drivers
        13. 6.3.10.13 Audio-Output Stage-Power Configurations
        14. 6.3.10.14 DAC Setup
        15. 6.3.10.15 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker Outputs
      11. 6.3.11 CLOCK Generation and PLL
        1. 6.3.11.1 PLL
      12. 6.3.12 Timer
      13. 6.3.13 Digital Audio and Control Interface
        1. 6.3.13.1 Digital Audio Interface
          1. 6.3.13.1.1 Right-Justified Mode
          2. 6.3.13.1.2 Left-Justified Mode
          3. 6.3.13.1.3 I2S Mode
          4. 6.3.13.1.4 DSP Mode
        2. 6.3.13.2 Primary and Secondary Digital Audio Interface Selection
        3. 6.3.13.3 Control Interface
          1. 6.3.13.3.1 I2C Control Mode
    4. 6.4 Register Map
      1. 6.4.1 Register Map
      2. 6.4.2 Registers
        1. 6.4.2.1 Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces, Flags, Interrupts, and GPIOs
          1. Table 6-31 Page 0 / Register 0 (0x00): Page Control Register
          2. Table 6-32 Page 0 / Register 1 (0x01): Software Reset
          3. Table 6-33 Page 0 / Register 2 (0x02): Reserved
          4. Table 6-34 Page 0 / Register 3 (0x03): OT FLAG
          5. Table 6-35 Page 0 / Register 4 (0x04): Clock-Gen Muxing
          6. Table 6-36 Page 0 / Register 5 (0x05): PLL P and R Values
          7. Table 6-37 Page 0 / Register 6 (0x06): PLL J-Value
          8. Table 6-38 Page 0 / Register 7 (0x07): PLL D-Value MSB
          9. Table 6-39 Page 0 / Register 8 (0x08): PLL D-Value LSB
          10. Table 6-40 Page 0 / Register 9 (0x09) and Page 0 / Register 10 (0x0A): Reserved
          11. Table 6-41 Page 0 / Register 11 (0x0B): DAC NDAC_VAL
          12. Table 6-42 Page 0 / Register 12 (0x0C): DAC MDAC_VAL
          13. Table 6-43 Page 0 / Register 13 (0x0D): DAC DOSR_VAL MSB
          14. Table 6-44 Page 0 / Register 14 (0x0E): DAC DOSR_VAL LSB
          15. Table 6-45 Page 0 / Register 15 (0x0F) through Page 0 / Register 24 (0x18): Reserved
          16. Table 6-46 Page 0 / Register 25 (0x19): CLKOUT MUX
          17. Table 6-47 Page 0 / Register 26 (0x1A): CLKOUT M_VAL
          18. Table 6-48 Page 0 / Register 27 (0x1B): Codec Interface Control 1
          19. Table 6-49 Page 0 / Register 28 (0x1C): Data-Slot Offset Programmability
          20. Table 6-50 Page 0 / Register 29 (0x1D): Codec Interface Control 2
          21. Table 6-51 Page 0 / Register 30 (0x1E): BCLK N_VAL
          22. Table 6-52 Page 0 / Register 31 (0x1F): Codec Secondary Interface Control 1
          23. Table 6-53 Page 0 / Register 32 (0x20): Codec Secondary Interface Control 2
          24. Table 6-54 Page 0 / Register 33 (0x21): Codec Secondary Interface Control 3
          25. Table 6-55 Page 0 / Register 34 (0x22): I2C Bus Condition
          26. Table 6-56 Page 0 / Register 35 (0x23) and Page 0 / Register 36 (0x24): Reserved
          27. Table 6-57 Page 0 / Register 37 (0x25): DAC Flag Register
          28. Table 6-58 Page 0 / Register 38 (0x26): DAC Flag Register
          29. Table 6-59 Page 0 / Register 39 (0x27): Overflow Flags
          30. Table 6-60 Page 0 / Register 40 (0x28) Through Page 0 / Register 43 (0x2B): Reserved
          31. Table 6-61 Page 0 / Register 44 (0x2C): DAC Interrupt Flags (Sticky Bits)
          32. Table 6-62 Page 0 / Register 45 (0x2D): Reserved
          33. Table 6-63 Page 0 / Register 46 (0x2E): Interrupt Flags—DAC
          34. Table 6-64 Page 0 / Register 47 (0x2F): Reserved
          35. Table 6-65 Page 0 / Register 48 (0x30): INT1 Control Register
          36. Table 6-66 Page 0 / Register 49 (0x31): INT2 Control Register
          37. Table 6-67 Page 0 / Register 50 (0x32): Reserved
          38. Table 6-68 Page 0 / Register 52 (0x34): Reserved
          39. Table 6-69 Page 0 / Register 53: Reserved
          40. Table 6-70 Page 0 / Register 54 (0x36): DIN (IN Pin) Control
          41. Table 6-71 Page 0 / Register 55 (0x37) through Page 0 / Register 59 (0x3B): Reserved
          42. Table 6-72 Page 0 / Register 60 (0x3C): DAC Processing Block Selection
          43. Table 6-73 Page 0 / Register 61 (0x3D)Through Page 0 / Register 62: Reserved
          44. Table 6-74 Page 0 / Register 63 (0x3F): DAC Data-Path Setup
          45. Table 6-75 Page 0 / Register 64 (0x40): DAC Volume Control
          46. Table 6-76 Page 0 / Register 65 (0x41): DAC Left Volume Control
          47. Table 6-77 Page 0 / Register 66 (0x42): DAC Right Volume Control
          48. Table 6-78 Page 0 / Register 67 (0x43): Headset Detection
          49. Table 6-79 Page 0 / Register 68 (0x44): DRC Control 1
          50. Table 6-80 Page 0 / Register 69 (0x45): DRC Control 2
          51. Table 6-81 Page 0 / Register 70 (0x46): DRC Control 3
          52. Table 6-82 Page 0 / Register 71 (0x47): Left Beep Generator
          53. Table 6-83 Page 0 / Register 72 (0x48): Right Beep Generator
          54. Table 6-84 Page 0 / Register 73 (0x49): Beep Length MSB
          55. Table 6-85 Page 0 / Register 74 (0x4A): Beep-Length Middle Bits
          56. Table 6-86 Page 0 / Register 75 (0x4B): Beep Length LSB
          57. Table 6-87 Page 0 / Register 76 (0x4C): Beep Sin(x) MSB
          58. Table 6-88 Page 0 / Register 77 (0x4D): Beep Sin(x) LSB
          59. Table 6-89 Page 0 / Register 78 (0x4E): Beep Cos(x) MSB
          60. Table 6-90 Page 0 / Register 79 (0x4F): Beep Cos(x) LSB
          61. Table 6-91 Page 0 / Register 80 (0x50) Through Page 0 / Register 115 (0x73): Reserved
          62. Table 6-92 Page 0 / Register 116 (0x74): VOL/MICDET-Pin SAR ADC — Volume Control
          63. Table 6-93 Page 0 / Register 117 (0x75): VOL/MICDET-Pin Gain
          64. Table 6-94 Page 0 / Register 118 (0x76) Through Page 0 / Register 127 (0x7F): Reserved
        2. 6.4.2.2 Control Registers, Page 1: DAC, Power-Controls, and MISC Logic-Related Programmability
          1. Table 6-95  Page 1 / Register 0 (0x00): Page Control Register
          2. Table 6-96  Page 1 / Register 1 (0x01) Through Page 1 / Register 29 (0x1D): Reserved
          3. Table 6-97  Page 1 / Register 30 (0x1E): Headphone and Speaker Amplifier Error Control
          4. Table 6-98  Page 1 / Register 31 (0x1F): Headphone Drivers
          5. Table 6-99  Page 1 / Register 32 (0x20): Class-D Speaker Amplifier
          6. Table 6-100 Page 1 / Register 33 (0x21): HP Output Drivers POP Removal Settings
          7. Table 6-101 Page 1 / Register 34 (0x22): Output Driver PGA Ramp-Down Period Control
          8. Table 6-102 Page 1 / Register 35 (0x23): DAC_L and DAC_R Output Mixer Routing
          9. Table 6-103 Page 1 / Register 36 (0x24): Left Analog Volume to HPL
          10. Table 6-104 Page 1 / Register 37 (0x25): Right Analog Volume to HPR
          11. Table 6-105 Page 1 / Register 38 (0x26): Left Analog Volume to SPL
          12. Table 6-106 Page 1 / Register 39 (0x27): Right Analog Volume to SPR
          13. Table 6-107 Page 1 / Register 40 (0x28): HPL Driver
          14. Table 6-108 Page 1 / Register 41 (0x29): HPR Driver
          15. Table 6-109 Page 1 / Register 42 (0x2A): SPL Driver
          16. Table 6-110 Page 1 / Register 43 (0x2B): SPR Driver
          17. Table 6-111 Page 1 / Register 44 (0x2C): HP Driver Control
          18. Table 6-112 Page 1 / Register 45 (0x2D): Reserved
          19. Table 6-113 Page 1 / Register 46 (0x2E): MICBIAS
          20. Table 6-114 Page 1 / Register 50 (0x32): Input CM Settings
          21. Table 6-115 Page 1 / Register 51 (0x33) Through Page 1 / Register 127 (0x7F): Reserved
        3. 6.4.2.3 Control Registers, Page 3: MCLK Divider for Programmable Delay Timer
          1. Table 6-116 Page 3 / Register 0 (0x00): Page Control Register
          2. Table 6-117 Page 3 / Register 16 (0x10): Timer Clock MCLK Divider
        4. 6.4.2.4 Control Registers, Page 8: DAC Programmable Coefficients RAM Buffer A (1:63)
          1. Table 6-118 Page 8 / Register 0 (0x00): Page Control Register
          2. Table 6-119 Page 8 / Register 1 (0x01): DAC Coefficient RAM Control
          3. Table 6-120 Page-8 DAC Buffer A Registers
        5. 6.4.2.5 Control Registers, Page 9: DAC Programmable Coefficients RAM Buffer A (65:127)
          1. Table 6-121 Page 9 / Register 0 (0x00): Page Control Register
          2. Table 6-122 Page-9 DAC Buffer A Registers
        6. 6.4.2.6 Control Registers, Page 12: DAC Programmable Coefficients RAM Buffer B (1:63)
          1. Table 6-1   Page 12 / Register 0 (0x00): Page Control Register
          2. Table 6-123 Page-12 AC Buffer B Registers
        7. 6.4.2.7 Control Registers, Page 13: DAC Programmable Coefficients RAM Buffer B (65:127)
          1. Table 6-2   Page 13 / Register 0 (0x00): Page Control Register
          2. Table 6-124 Page-13 DAC Buffer B Registers
  7. 7Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
  8. 8Power Supply Recommendations
  9. 9Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.10.3 Volume Control Pin

The volume-control pin is not enabled by default but is enabled by writing 1 to page 0 / register 116, bit D7. The default DAC volume control uses software control of the volume, which occurs if page 0 / register 116, bit D7 = 0. Soft-stepping the volume level is set up by writing to page 0 / register 63, bits D1–D0.

When the volume-pin function is used, a 7-bit Vol ADC reads the voltage on the VOL/MICDET pin and updates the digital volume control by overwriting the current value of the volume control. The new volume setting which has been applied because of a change of voltage on the volume control pin is read on page 0 / register 117, bits D6–D0. The 7-bit Vol ADC clock source is selected on page 0 / register 116, bit D6. The update rate is programmed on page 0 / register 116, bits D2–D0 for this 7-bit SAR ADC.

Table 6-18 lists The VOL/MICDET pin gain mapping.

Table 6-18 VOL/MICDET Pin Gain Mapping

VOL/MICDET PIN SAR OUTPUT DIGITAL GAIN APPLIED
0 18 dB
1 17.5 dB
2 17 dB
: :
35 0.5 dB
36 0.0 dB
37 –0.5 dB
: :
89 –26.5 dB
90 –27 dB
91 –28 dB
: :
125 –62 dB
126 –63 dB
127 Mute

Figure 6-16 shows the VOL/MICDET pin connection and functionality.

TLV320DAC3101 B0210-05_LAS550.gifFigure 6-16 Digital Volume Controls for Beep Generator and DAC Play Data

As shown in Table 6-18, the VOL/MICDET pin has a range of volume control from 18 dB down to –63 dB, and mute. However, if less maximum gain is required, then a smaller range of voltage must be applied to the VOL/MICDET pin. Applying a smaller range of voltage occurs by increasing the value of R2 relative to the value of (P1 + R1), so that more voltage is available at the bottom of P1. The circuit must also be designed such that for the values of R1, R2, and P1 chosen, the maximum voltage (top of the potentiometer) does not exceed AVDD/2 (see Figure 6-16). The recommended values for R1, R2, and P1 for several maximum gains are shown in Table 6-19.

Table 6-19 VOL/MICDET Pin Gain Scaling

R1
(kΩ)		 P1
(kΩ)		 R2
(kΩ)		 ADC VOLTAGE
for AVDD = 3.3 V
(V)		 DIGITAL GAIN RANGE
(dB)
25 25 0 0 to 1.65 18 to –63
33 25 7.68 0.386 to 1.642 3 to –63
34.8 25 9.76 0.463 to 1.649 0 to –63