SBVS151F December   2010  – April 2017 TLV705 , TLV705P

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Undervoltage Lockout (UVLO)
      3. 7.3.3 Start-Up Current
      4. 7.3.4 Dropout Voltage
      5. 7.3.5 Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input and Output Capacitor Requirements
        2. 8.2.2.2 Transient Response
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
    4. 10.4 Power Dissipation and Junction Temperature
    5. 10.5 Estimating Junction Temperature
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Mounting

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

specified at TJ = –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND.(1)
MIN MAX UNIT
Voltage(2) VIN –0.3 6 V
VEN –0.3 6 V
VOUT –0.3 6 V
Maximum output current IOUT Internally limited
Output short-circuit duration Indefinite
Temperature Operating junction, TJ –55 150 °C
Storage, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground pin.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage 2 5.5 V
VOUT Output voltage 0.7 4.8 V
IOUT Output current 0 200 mA
TJ Junction temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TLV705 UNIT
YFF, YFP
(DSBGA)		 YFM
(PicoStar)
4 PINS 4 PINS
RθJA Junction-to-ambient thermal resistance 160 191.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 80 3.1 °C/W
RθJB Junction-to-board thermal resistance 90 36.5 °C/W
ψJT Junction-to-top characterization parameter 0.5 2.8 °C/W
ψJB Junction-to-board characterization parameter 78 26.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA, VEN = 0.9 V, and
COUT = 1 μF, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range 2 5.5 V
VOUT Output voltage range 0.7 4.8 V
VO DC output accuracy –40°C ≤ TJ ≤ 125°C 0 mA ≤ IOUT ≤ 200 mA, VOUT ≥ 1 V –2% ±0.5% 2%
0 mA ≤ IOUT ≤ 200 mA, VOUT < 1 V –20 ±5 20 mV
ΔVOUT(ΔVIN) Line regulation VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V 0.05 5 mV
ΔVOUT(ΔIOUT) Load regulation 0 mA ≤ IOUT ≤ 200 mA 1 mV
VDO Dropout voltage(1) VIN = 0.98 × VOUT(nom), IOUT = 200 mA 145 250 mV
ICL Output current limit VOUT = 0.9 × VOUT(nom), TJ = 25°C 260 400 550 mA
IGND Ground pin current IOUT = 0 mA 35 55 μA
IOUT = 200 mA 315 μA
ISHUTDOWN Shutdown ground pin current VEN ≤ 0.4 V, 2 V ≤ VIN ≤ 4.5 V 1 1.8 μA
PSRR Power-supply rejection ratio VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA,
f = 10 kHz		 80 dB
VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA,
f = 1 MHz		 55 dB
Vn Output noise voltage BW = 100 Hz to
100 kHz, IOUT = 10 mA		 VIN = 2.3 V, VOUT = 1.8 V 26.6 μVRMS
VIN = 3.3 V, VOUT = 2.8 V 26.7 μVRMS
VIN = 3.8 V, VOUT = 3.3 V 28.2 μVRMS
BW = 10 Hz to 100 kHz, IOUT = 10 mA VIN = 2.3 V, VOUT = 1.8 V 30.7 μVRMS
VIN = 3.3 V, VOUT = 2.8 V 31.3 μVRMS
VIN = 3.8 V, VOUT = 3.3 V 34.1 μVRMS
tSTR Start-up time(2) COUT = 1 μF, IOUT = 200 mA 100 μs
VHI Enable high (enabled) 0.9 VIN V
VLO Enable low (disabled) 0 0.4 V
IEN EN pin current VEN = 5.5 V 0.01 μA
UVLO Undervoltage lockout VIN rising 1.9 V
tSD Thermal shutdown temperature Shutdown, temperature increasing 160 °C
Reset, temperature decreasing 140 °C
TJ Operating junction temperature –40 125 °C
(1) VDO is measured for devices with VOUT(nom) = 2.35 V so that VIN = 2.3 V.
(2) Start-up time = time from EN assertion to 0.98 × VOUT(nom).

6.6 Typical Characteristics

over operating temperature range (TJ = –40°C to +125°C), IOUT = 10 mA, VEN = 0.9 V, COUT = 1 μF, and VIN = VOUT(nom) + 0.5 V or 2 V, whichever is greater, unless otherwise noted. Typical values are at TJ = 25°C.
TLV705 TLV705P tc_line_reg_10ma_bvs151.gif
Figure 1. Line Regulation
TLV705 TLV705P tc_load_reg_bvs151.gif
Figure 3. Load Regulation ( 0 mA ≤ IOUT ≤ 200 mA)
TLV705 TLV705P tc_vdo-iout_bvs151.gif
Figure 5. Dropout Voltage vs Output Current
TLV705 TLV705P tc_ignd-vin_bvs151.gif
Figure 7. Ground Pin Current vs Input Voltage
TLV705 TLV705P tc_ignd-tmp_bvs151.gif
Figure 9. Ground Pin Current vs Temperature
TLV705 TLV705P tc_ilim-vin_bvs151.gif
Figure 11. Current Limit vs Input Voltage
TLV705 TLV705P tc_psrr-vin_bvs151.gif
Figure 13. Power-Supply Rejection Ratio vs Input Voltage
TLV705 TLV705P tc_int_noise-vo_bvs151.gif
Figure 15. Integrated Noise vs Output Voltage
TLV705 TLV705P tc_load_trans_1_bvs151.gif
Figure 17. Load Transient 1
TLV705 TLV705P tc_sm_line_trans_10ma_bvs151.gif
Figure 19. Small-Step Line Transient (10 mA)
TLV705 TLV705P tc_vin_curr_0ma_bvs151.gif
Figure 21. VIN Inrush Current
TLV705 TLV705P tc_line_trans_10ma_bvs151.gif
Figure 23. Line Transient (10 mA)
TLV705 TLV705P tc_pwr_updwn_bvs151.gif
Figure 25. Power-Up and Power-Down
TLV705 TLV705P tc_line_reg_200ma_bvs151.gif
Figure 2. Line Regulation
TLV705 TLV705P tc_vdo-vin_bvs151.gif
Figure 4. Dropout Voltage vs Input Voltage
TLV705 TLV705P tc_vout-tmp_bvs151.gif
Figure 6. Output Voltage vs Temperature
TLV705 TLV705P tc_ignd_iout_bvs151.gif
Figure 8. Ground Pin Current vs Output Current
TLV705 TLV705P tc_ishdn-vin_bvs151.gif
Figure 10. Shutdown Pin Current vs Input Voltage
TLV705 TLV705P tc_psrr-frq_bvs151.gif
Figure 12. Power-Supply Rejection Ratio vs Frequency
TLV705 TLV705P tc_spec_noise-frq_bvs151.gif
Figure 14. Output Spectral Noise Density vs Frequency
TLV705 TLV705P tc_load_trans_0_bvs151.gif
Figure 16. Load Transient 0
TLV705 TLV705P tc_load_trans_3_bvs151.gif
Figure 18. Load Transient 3
TLV705 TLV705P tc_sm_line_trans_200ma_bvs151.gif
Figure 20. Small-Step Line Transient (200 mA)
TLV705 TLV705P tc_vin_curr_200ma_bvs151.gif
Figure 22. VIN Inrush Current
TLV705 TLV705P tc_line_trans_200ma_bvs151.gif
Figure 24. Line Transient (200 mA)