SBVS157C April   2011  – September 2015 TLV803 , TLV853

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Thermal Information
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD Transient Rejection
      2. 8.3.2 Reset During Power Up and Power Down
      3. 8.3.3 Bidirectional Reset Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > Power-Up Reset Voltage)
      2. 8.4.2 Power On Reset (VDD < Power-Up Reset Voltage)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Monitoring Multiple Supplies
      2. 9.1.2 Output Level Shifting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Evaluation Modules
        2. 12.1.1.2 Spice Models
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating junction temperature range (unless otherwise noted)
MIN MAX UNIT
Voltage VDD(2) 0 7 V
All other pins(2) –0.3 +7
Current Maximum low output current, IOL 5 mA
Maximum high output current, IOH –5
Input clamp current, IIK (VI < 0 or VI > VDD) ±20
Output clamp current, IOK (VO < 0 or VO > VDD) ±20
Temperature Operating junction temperature range, TJ –40 125 °C
Storage temperature range, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND. For reliable operation the device should not be operated at 7 V for more than t = 1000h continuously

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Thermal Information

THERMAL METRIC(1) TLV8x3 UNITS
DBZ (SOT-23)
3 PINS
RθJA Junction-to-ambient thermal resistance 328.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 135.4 °C/W
RθJB Junction-to-board thermal resistance 58.3 °C/W
ψJT Junction-to-top characterization parameter 5.2 °C/W
ψJB Junction-to-board characterization parameter 59.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.4 Recommended Operating Conditions

at specified temperature range (unless otherwise noted)
MIN MAX UNIT
VDD Supply voltage 1.1 6 V
TJ Operating junction temperature –40 125 °C

7.5 Electrical Characteristics

over recommended operating junction temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOL Low-level output voltage VDD = 2 V to 6 V, IOL = 500 µA 0.2 V
VDD = 3.3 V, IOL = 2 mA 0.4
VDD = 6 V, IOL = 4 mA 0.4
Power-up reset voltage(1) IOL = 50 µA, VOL < 0.2 V 1.1 V
VIT– Negative-going input threshold voltage(2) TLV803Z TJ = – 40°C to +125°C 2.20 2.25 2.30 V
TLV803R 2.58 2.64 2.70
TLV803S 2.87 2.93 2.99
TLV8x3M 4.28 4.38 4.48
Vhys Hysteresis TLV803Z TJ = 25°C, IOL = 50 µA 30 mV
TLV803R 35
TLV803S 40
TLV8x3M 60
IDD Supply current VDD = 2 V, output unconnected 9 15 µA
VDD = 6 V, output unconnected 20 30
IOH Output leakage current VDD = 6 V 100 nA
(1) The lowest supply voltage at which RESET becomes valid. tr,VDD ≤ 66.7 V/ms.
(2) To ensure best stability of the threshold voltage, place a bypass capacitor (0.1-µF ceramic) near the supply terminals.

7.6 Switching Characteristics

over operating temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tw Pulse duration at VDD VDD = 1.08 VIT– to 0.92 VIT– 1 µs
td Delay time VDD ≥ VIT– + 0.2 V; see Timing Diagram 120 200 280 ms
TLV803 TLV853 TLV863 tim_bvs157.gif Figure 1. Timing Diagram

7.7 Typical Characteristics

at TJ = 25°C, VIT– = 4.38 V, and VDD = 5.0 V (unless otherwise noted)
TLV803 TLV853 TLV863 tc_vol-iol_bvs157.gif
Figure 2. Low-Level Output Voltage vs Low-Level Output Current
TLV803 TLV853 TLV863 tc_vit-tmp_bvs157.gif
Figure 4. Normalized to 25°C Negative-Going Input Threshold Voltage vs Temperature
TLV803 TLV853 TLV863 tc_td-tmp_bvs157.gif
Figure 6. Delay Time vs Temperature
TLV803 TLV853 TLV863 tc_idd-vdd_bvs157.gif
Figure 3. Supply Current vs Supply Voltage
TLV803 TLV853 TLV863 tc_pulse-overdrive_bvs157.gif
Figure 5. Minimum Pulse Duration At VDD vs Overdrive Voltage
TLV803 TLV853 TLV863 tc_vol-vdd_bvs157.gif
Figure 7. Power-Up Low-Level Output Voltage vs Supply Voltage