SBOS839J March   2017  – September 2019 TLV9061 , TLV9062 , TLV9064

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Single-Pole, Low-Pass Filter
      2.      Small-Signal Overshoot vs Load Capacitance
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions: TLV9061
    2.     Pin Functions: TLV9061S
    3.     Pin Functions: TLV9062
    4.     Pin Functions: TLV9062S
    5.     Pin Functions: TLV9064
    6.     Pin Functions: TLV9064S
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information: TLV9061
    5. 8.5  Thermal Information: TLV9061S
    6. 8.6  Thermal Information: TLV9062
    7. 8.7  Thermal Information: TLV9062S
    8. 8.8  Thermal Information: TLV9064
    9. 8.9  Thermal Information: TLV9064S
    10. 8.10 Electrical Characteristics
    11. 8.11 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Rail-to-Rail Input
      2. 9.3.2 Rail-to-Rail Output
      3. 9.3.3 EMI Rejection
      4. 9.3.4 Overload Recovery
      5. 9.3.5 Shutdown Function
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Typical Low-Side Current Sense Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Input and ESD Protection
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.10 Electrical Characteristics

For VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VS = 5 V ±0.3 ±1.6 mV
VS = 5 V, TA = –40°C to 125°C ±2
dVOS/dT Drift VS = 5 V, TA = –40°C to 125°C ±0.53 µV/°C
PSRR Power-supply rejection ratio VS = 1.8 V – 5.5 V, VCM = (V–) ±7 ±80 µV/V
Channel separation, DC At DC 100 dB
INPUT VOLTAGE RANGE
VCM Common-mode voltage range VS = 1.8 V to 5.5 V (V–) – 0.1 (V+) + 0.1 V
CMRR Common-mode rejection ratio VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
TA = –40°C to 125°C 		80 103 dB
VS = 5.5 V, VCM = –0.1 V to 5.6 V,
TA = –40°C to 125°C 		57 87
VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
TA = –40°C to 125°C 		88
VS = 1.8 V, VCM = –0.1 V to 1.9 V,
TA = –40°C to 125°C		 81
INPUT BIAS CURRENT
IB Input bias current ±0.5 pA
IOS Input offset current ±0.05 pA
NOISE
En Input voltage noise (peak-to-peak) VS = 5 V, f = 0.1 Hz to 10 Hz 4.77 µVPP
en Input voltage noise density VS = 5 V, f = 10 kHz 10 nV/√Hz
VS = 5 V, f = 1 kHz 16
in Input current noise density f = 1 kHz 23 fA/√Hz
INPUT CAPACITANCE
CID Differential 2 pF
CIC Common-mode 4 pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V,
RL = 10 kΩ		 100 dB
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ		 104 130
VS = 1.8 V, (V–) + 0.06 V < VO < (V+) – 0.06 V,
RL = 2 kΩ		 100
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ		 130
FREQUENCY RESPONSE
GBP Gain bandwidth product VS = 5 V, G = +1 10 MHz
φm Phase margin VS = 5 V, G = +1 55 °
SR Slew rate VS = 5 V, G = +1 6.5 V/µs
tS Settling time To 0.1%, VS = 5 V, 2-V step , G = +1, CL = 100 pF 0.5 µs
To 0.01%, VS = 5 V, 2-V step,
G = +1, CL = 100 pF		 1
tOR Overload recovery time VS = 5 V, VIN × gain > VS 0.2 µs
THD + N Total harmonic distortion + noise(1) VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1,
f = 1 kHz 		0.0008%
OUTPUT
VO Voltage output swing from supply rails VS = 5.5 V, RL = 10 kΩ 20 mV
VS = 5.5 V, RL = 2 kΩ 60
ISC Short-circuit current VS = 5 V ±50 mA
ZO Open-loop output impedance VS = 5 V, f = 10 MHz 100 Ω
POWER SUPPLY
IQ Quiescent current per amplifier VS = 5.5 V, IO = 0 mA 538 750 µA
VS = 5.5 V, IO = 0 mA, TA = –40°C to 125°C 800
SHUTDOWN
IQSD Quiescent current per amplifier VS = 1.8 V to 5.5 V, all amplifiers disabled,
SHDN = Low		 0.5 1.5 µA
ZSHDN Output impedance during shutdown VS = 1.8 V to 5.5 V, amplifier disabled 10 || 8 GΩ || pF
VSHDN_THR_HI High level voltage shutdown threshold (amplifier enabled) VS = 1.8 V to 5.5 V (V–) + 0.9 V (V–) + 1.1 V V
VSDHN_THR_LO Low level voltage shutdown threshold (amplifier disabled) VS = 1.8 V to 5.5 V (V–) + 0.2 V (V–) + 0.7 V V
tON Amplifier enable time (shutdown)(2) VS = 1.8 V to 5.5 V, full shutdown; G = 1,
VOUT = 0.9 × VS / 2, RL connected to V–		 10 µs
tOFF Amplifier disable time(2) VS = 1.8 V to 5.5 V, G = 1, VOUT = 0.1 × VS / 2,
RL connected to V–		 0.6 µs
SHDN pin input bias current (per pin) VS = 1.8 V to 5.5 V, V+ ≥ SHDN ≥ (V+) – 0.8 V 130 pA
VS = 1.8 V to 5.5 V, V– ≤ SHDN ≤ V– + 0.8 V 40
(1) Third-order filter; bandwidth = 80 kHz at –3 dB.
(2) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.