SBOS397H August 2007 – December 2018 TMP102
PRODUCTION DATA.
FAST MODE | HIGH-SPEED MODE | UNIT | |||||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
ƒ(SCL) | SCL operating frequency | V+ | 0.001 | 0.4 | 0.001 | 2.85 | MHz | ||
t(BUF) | Bus-free time between STOP and START condition | See Figure 7 | 600 | 160 | ns | ||||
t(HDSTA) | Hold time after repeated START condition.
After this period, the first clock is generated. |
600 | 160 | ns | |||||
t(SUSTA) | repeated start condition setup time | 600 | 160 | ns | |||||
t(SUSTO) | STOP condition setup time | 600 | 160 | ns | |||||
t(HDDAT) | Data hold time | 100 | 900 | 25 | 105 | ns | |||
t(SUDAT) | Data setup time | 100 | 25 | ns | |||||
t(LOW) | SCL-clock low period | V+ , see Figure 7 | 1300 | 210 | ns | ||||
t(HIGH) | SCL-clock high period | See Figure 7 | 600 | 60 | ns | ||||
tFD | Data fall time | See Figure 7 | 300 | 80 | ns | ||||
tRD | Data rise time | See Figure 7 | 300 | ns | |||||
SCLK ≤ 100 kHz, see Figure 7 | 1000 | ns | |||||||
tFC | Clock fall time | See Figure 7 | 300 | 40 | ns | ||||
tRC | Clock rise time | See Figure 7 | 300 | 40 | ns |