SPRS867A February   2013  – August 2016 TMS320DM369

PRODUCTION DATA.  

  1. 1TMS320DM369 Digital Media System-on-Chip (DMSoC)
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Overview
    1. 3.1 Device Comparison
    2. 3.2 Device Characteristics
    3. 3.3 Device Compatibility
    4. 3.4 ARM Subsystem Overview
      1. 3.4.1  Components of the ARM Subsystem
      2. 3.4.2  ARM926EJ-S RISC CPU
      3. 3.4.3  CP15
      4. 3.4.4  MMU
      5. 3.4.5  Caches and Write Buffer
      6. 3.4.6  Tightly Coupled Memory (TCM)
      7. 3.4.7  Advanced High-performance Bus (AHB)
      8. 3.4.8  Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
      9. 3.4.9  ARM Memory Mapping
        1. 3.4.9.1 ARM Internal Memories
        2. 3.4.9.2 External Memories
      10. 3.4.10 Peripherals
      11. 3.4.11 ARM Interrupt Controller (AINTC)
    5. 3.5 System Control Module
    6. 3.6 Power Management
    7. 3.7 Memory Map Summary
    8. 3.8 Pin Assignments
      1. 3.8.1 Pin Map (Bottom View)
    9. 3.9 Terminal Functions
  4. 4Device Configurations
    1. 4.1 System Module Registers
    2. 4.2 Boot Modes
      1. 4.2.1 Boot Modes Overview
    3. 4.3 Device Clocking
      1. 4.3.1 Overview
      2. 4.3.2 PLL Controller Module
      3. 4.3.3 PLLC1
      4. 4.3.4 PLLC2
      5. 4.3.5 Processing, Video, EDMA and DDR EMIF Subsystems Maximum Operating Frequencies
      6. 4.3.6 PLL Controller Clocking Configurations Examples
      7. 4.3.7 Peripheral Clocking Considerations
    4. 4.4 Power and Sleep Controller (PSC)
    5. 4.5 Pin Multiplexing
    6. 4.6 Device Reset
    7. 4.7 Default Device Configurations
      1. 4.7.1 Device Configuration Pins
      2. 4.7.2 PLL Configuration
      3. 4.7.3 Power Domain and Module State Configuration
      4. 4.7.4 ARM Boot Mode Configuration
      5. 4.7.5 AEMIF Configuration
        1. 4.7.5.1 AEMIF Pin Configuration
        2. 4.7.5.2 AEMIF Timing Configuration
      6. 4.7.6 Oscillator Frequency Configuration
    8. 4.8 Debugging Considerations
      1. 4.8.1 Pullup/Pulldown Resistors
  5. 5System Interconnect
  6. 6Device Operating Conditions
    1. 6.1 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1  Parameter Information Device-Specific Information
      1. 7.1.1 Signal Transition Levels
      2. 7.1.2 Timing Parameters and Board Routing Analysis
    2. 7.2  Recommended Clock and Control Signal Transition Behavior
    3. 7.3  Power Supplies
    4. 7.4  Power-Supply Sequencing
      1. 7.4.1 Simple Power-On and Power-Off Method
      2. 7.4.2 Restricted Power-On and Power-Off Method
      3. 7.4.3 Power-Supply Design Considerations
      4. 7.4.4 Power-Supply Decoupling
    5. 7.5  Reset
      1. 7.5.1 Reset Electrical Data/Timing
    6. 7.6  Oscillators and Clocks
      1. 7.6.1 MXI1 Oscillator
      2. 7.6.2 Clock PLL Electrical Data/Timing (Input and Output Clocks)
      3. 7.6.3 PRTCSS Oscillator
      4. 7.6.4 PRTCSS Electrical Data/Timing
    7. 7.7  Power Management and Real Time Clock Subsystem (PRTCSS)
      1. 7.7.1 PRTCSS Peripheral Register Description
    8. 7.8  General-Purpose Input/Output (GPIO)
      1. 7.8.1 GPIO Peripheral Register Description
      2. 7.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
      3. 7.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
    9. 7.9  EDMA Controller
      1. 7.9.1 EDMA Channel Synchronization Events
      2. 7.9.2 EDMA Peripheral Register Description
    10. 7.10 External Memory Interface (EMIF)
      1. 7.10.1 Asynchronous EMIF (AEMIF)
        1. 7.10.1.1 NAND (NAND, SmartMedia, xD)
        2. 7.10.1.2 OneNAND
        3. 7.10.1.3 EMIF Peripheral Register Descriptions
        4. 7.10.1.4 AEMIF Electrical Data/Timing
      2. 7.10.2 DDR2/mDDR Memory Controller
      3. 7.10.3 DDR2/mDDR Memory Controller Electrical Data/Timing
        1. 7.10.3.1 DDR2/mDDR Routing Specifications
          1. 7.10.3.1.1  DDR2/mDDR Interface
          2. 7.10.3.1.2  DDR2/mDDR Interface Schematic
          3. 7.10.3.1.3  Compatible JEDEC DDR2/mDDR Devices
          4. 7.10.3.1.4  PCB Stack Up
          5. 7.10.3.1.5  Placement
          6. 7.10.3.1.6  DDR2/mDDR Keep Out Region
          7. 7.10.3.1.7  Bulk Bypass Capacitors
          8. 7.10.3.1.8  High-Speed Bypass Capacitors
          9. 7.10.3.1.9  Net Classes
          10. 7.10.3.1.10 DDR2/mDDR Signal Termination
          11. 7.10.3.1.11 VREF Routing
          12. 7.10.3.1.12 DDR2/mDDR CK and ADDR_CTRL Routing
    11. 7.11 MMC/SD
      1. 7.11.1 MMC/SD Peripheral Register Description
      2. 7.11.2 MMC/SD Electrical Data/Timing
    12. 7.12 Video Processing Subsystem (VPSS) Overview
      1. 7.12.1 Video Processing Front-End (VPFE)
        1. 7.12.1.1 Image Sensor Interface (ISIF)
        2. 7.12.1.2 The Image Pipe Interface (IPIPEIF)
        3. 7.12.1.3 Image Pipe - Hardware Image Signal Processor (IPIPE)
        4. 7.12.1.4 Hardware 3A (H3A)
        5. 7.12.1.5 Face Detection Module
        6. 7.12.1.6 VPFE Electrical Data/Timing
      2. 7.12.2 Video Processing Back-End (VPBE)
        1. 7.12.2.1 On-Screen Display (OSD)
        2. 7.12.2.2 Video Encoder / Digital LCD Controller (VENC/DLCD)
        3. 7.12.2.3 VPBE Electrical Data/Timing
        4. 7.12.2.4 High-Definition (HD) DACs and Video Buffer Electrical Data/Timing
          1. 7.12.2.4.1 HD DACs-Only Option
          2. 7.12.2.4.2 DAC With Video Buffer Option
    13. 7.13 USB2.0
      1. 7.13.1 USB Peripheral Register Description
      2. 7.13.2 USB2.0 Electrical Data/Timing
    14. 7.14 Universal Asynchronous Receiver/Transmitter (UART)
      1. 7.14.1 UART Peripheral Register Description
      2. 7.14.2 UART Electrical Data/Timing
    15. 7.15 Serial Port Interface (SPI)
      1. 7.15.1 SPI Peripheral Register Description
      2. 7.15.2 SPI Electrical Data/Timing
        1. 7.15.2.1 Master Mode — General
        2. 7.15.2.2 Slave Mode — General
        3. 7.15.2.3 Master Mode — Additional
        4. 7.15.2.4 Slave Mode — Additional
    16. 7.16 Inter-Integrated Circuit (I2C)
      1. 7.16.1 I2C Peripheral Register Description
      2. 7.16.2 I2C Electrical Data/Timing
        1. 7.16.2.1 Inter-Integrated Circuits (I2C) Timing
    17. 7.17 Multichannel Buffered Serial Port (McBSP)
      1. 7.17.1 McBSP Peripheral Register Description
      2. 7.17.2 McBSP Electrical Data/Timing
        1. 7.17.2.1 multichannel Buffered Serial Port (McBSP) Timing
    18. 7.18 Timer
      1. 7.18.1 Timer Peripheral Register Description
      2. 7.18.2 Timer Electrical Data/Timing
    19. 7.19 Pulse Width Modulator (PWM)
      1. 7.19.1 PWM Peripheral Register Description
      2. 7.19.2 PWM0/1/2/3 Electrical/Timing Data
    20. 7.20 Real Time Out (RTO)
      1. 7.20.1 Real Time Out (RTO) Peripheral Register Description
      2. 7.20.2 RTO Electrical/Timing Data
    21. 7.21 Ethernet Media Access Controller (EMAC)
      1. 7.21.1 EMAC Peripheral Register Description
      2. 7.21.2 Ethernet Media Access Controller (EMAC) Electrical Data/Timing
    22. 7.22 Management Data Input/Output (MDIO)
      1. 7.22.1 MDIO Peripheral Register Description
      2. 7.22.2 Management Data Input/Output (MDIO) Electrical Data/Timing
    23. 7.23 Host-Port Interface (HPI) Peripheral
      1. 7.23.1 HPI Device-Specific Information
      2. 7.23.2 HPI Bus Master
      3. 7.23.3 HPI Peripheral Register Description
      4. 7.23.4 HPI Electrical Data/Timing
    24. 7.24 Key Scan
      1. 7.24.1 Key Scan Peripheral Register Description
        1. 7.24.1.1 Key Scan Registers
      2. 7.24.2 Key Scan Electrical Data/Timing
    25. 7.25 Analog-to-Digital Converter (ADC)
      1. 7.25.1 Analog-to-Digital Converter (ADC) Peripheral Register Description
        1. 7.25.1.1 Analog-to-Digital Converter (ADC) Interface Registers
    26. 7.26 Voice Codec
      1. 7.26.1 Voice Codec Register Description
        1. 7.26.1.1 Voice Codec Registers
    27. 7.27 IEEE 1149.1 JTAG
      1. 7.27.1 JTAG Register Description
      2. 7.27.2 JTAG Test-Port Electrical Data/Timing
  8. 8Device and Documentation Support
    1. 8.1 Development Tools
    2. 8.2 Device Nomenclature
    3. 8.3 Documentation Support
    4. 8.4 Community Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information
    2. 9.2 Thermal Data for ZCE

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZCE|338
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 System Interconnect

The device uses a 64-bit crossbar architecture to control access between device processors, subsystems and peripherals. There are eleven transfer masters (TCs have separate read and write connections) connected to the crossbar; ARM, the Video Processing Subsystem (VPSS), the master peripherals (USB, EMAC, HPI), and four EDMA transfer controllers. These can be connected to seven separate slave ports; ARM, the DDR EMIF, CFG bus peripherals, MJCP, and HDVICP. Not all masters may connect to all slaves. Connection paths are indicated by √ at intersection points shown in Table 5-1.

Table 5-1 System Connection Matrix

SLAVE MODULE
DMA
Master		 ARM Internal
Memory		 MPEG/JPEG
Coprocessor Memory		 HD Video Image
Coprocessor
Memory		 Config Bus Registers
and
Memory		 DDR EMIF
Memory
ARM √ √ √ √ √
VPSS √ √
DMA Master Peripherals (USB, EMAC, HPI) √ √
EDMA3TC0 √ √ √ √ √
EDMA3TC1 √ √ √ √ √
EDMA3TC2 √ √ √ √ √
EDMA3TC3 √ √ √ √ √