SPRS584M April   2009  – January 2019 TMS320F28030 , TMS320F28031 , TMS320F28032 , TMS320F28033 , TMS320F28034 , TMS320F28035

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Automotive
    3. 5.3  ESD Ratings – Commercial
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F2803x Current Consumption at 60-MHz SYSCLKOUT
      2. 5.5.1     Reducing Current Consumption
      3. 5.5.2     Current Consumption Graphs (VREG Enabled)
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PN Package
      2. 5.7.2 PAG Package
      3. 5.7.3 RSH Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  Emulator Connection Without Signal Buffering for the MCU
    10. 5.10 Parameter Information
      1. 5.10.1 Timing Parameter Symbology
      2. 5.10.2 General Notes on Timing Parameters
    11. 5.11 Test Load Circuit
    12. 5.12 Power Sequencing
      1. Table 5-3 Reset (XRS) Timing Requirements
      2. Table 5-4 Reset (XRS) Switching Characteristics
    13. 5.13 Clock Specifications
      1. 5.13.1 Device Clock Table
        1. Table 5-5 2803x Clock Table and Nomenclature (60-MHz Devices)
        2. Table 5-6 Device Clocking Requirements/Characteristics
        3. Table 5-7 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
      2. 5.13.2 Clock Requirements and Characteristics
        1. Table 5-8  XCLKIN Timing Requirements – PLL Enabled
        2. Table 5-9  XCLKIN Timing Requirements – PLL Disabled
        3. Table 5-10 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 5.14 Flash Timing
      1. Table 5-11 Flash/OTP Endurance for T Temperature Material
      2. Table 5-12 Flash/OTP Endurance for S Temperature Material
      3. Table 5-13 Flash/OTP Endurance for Q Temperature Material
      4. Table 5-14 Flash Parameters at 60-MHz SYSCLKOUT
      5. Table 5-15 Flash/OTP Access Timing
      6. Table 5-16 Flash Data Retention Duration
  6. 6Detailed Description
    1. 6.1 Overview
      1. 6.1.1  CPU
      2. 6.1.2  Control Law Accelerator (CLA)
      3. 6.1.3  Memory Bus (Harvard Bus Architecture)
      4. 6.1.4  Peripheral Bus
      5. 6.1.5  Real-Time JTAG and Analysis
      6. 6.1.6  Flash
      7. 6.1.7  M0, M1 SARAMs
      8. 6.1.8  L0 SARAM, and L1, L2, and L3 DPSARAMs
      9. 6.1.9  Boot ROM
        1. 6.1.9.1 Emulation Boot
        2. 6.1.9.2 GetMode
        3. 6.1.9.3 Peripheral Pins Used by the Bootloader
      10. 6.1.10 Security
      11. 6.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 6.1.12 External Interrupts (XINT1–XINT3)
      13. 6.1.13 Internal Zero Pin Oscillators, Oscillator, and PLL
      14. 6.1.14 Watchdog
      15. 6.1.15 Peripheral Clocking
      16. 6.1.16 Low-power Modes
      17. 6.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 6.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 6.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 6.1.20 Control Peripherals
      21. 6.1.21 Serial Port Peripherals
    2. 6.2 Memory Maps
    3. 6.3 Register Maps
    4. 6.4 Device Emulation Registers
    5. 6.5 VREG/BOR/POR
      1. 6.5.1 On-chip Voltage Regulator (VREG)
        1. 6.5.1.1 Using the On-chip VREG
        2. 6.5.1.2 Disabling the On-chip VREG
      2. 6.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
    6. 6.6 System Control
      1. 6.6.1 Internal Zero Pin Oscillators
      2. 6.6.2 Crystal Oscillator Option
      3. 6.6.3 PLL-Based Clock Module
      4. 6.6.4 Loss of Input Clock (NMI Watchdog Function)
      5. 6.6.5 CPU-Watchdog Module
    7. 6.7 Low-power Modes Block
    8. 6.8 Interrupts
      1. 6.8.1 External Interrupts
        1. 6.8.1.1 External Interrupt Electrical Data/Timing
          1. Table 6-22 External Interrupt Timing Requirements
          2. Table 6-23 External Interrupt Switching Characteristics
    9. 6.9 Peripherals
      1. 6.9.1  Control Law Accelerator (CLA) Overview
      2. 6.9.2  Analog Block
        1. 6.9.2.1 Analog-to-Digital Converter (ADC)
          1. 6.9.2.1.1 Features
          2. 6.9.2.1.2 ADC Start-of-Conversion Electrical Data/Timing
            1. Table 6-28 External ADC Start-of-Conversion Switching Characteristics
          3. 6.9.2.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. Table 6-29  ADC Electrical Characteristics
            2. Table 6-30  ADC Power Modes
            3. 6.9.2.1.3.1 Internal Temperature Sensor
              1. Table 6-31 Temperature Sensor Coefficient
            4. 6.9.2.1.3.2 ADC Power-Up Control Bit Timing
              1. Table 6-32 ADC Power-Up Delays
            5. 6.9.2.1.3.3 ADC Sequential and Simultaneous Timings
        2. 6.9.2.2 ADC MUX
        3. 6.9.2.3 Comparator Block
          1. 6.9.2.3.1 On-Chip Comparator/DAC Electrical Data/Timing
            1. Table 6-34 Electrical Characteristics of the Comparator/DAC
      3. 6.9.3  Detailed Descriptions
      4. 6.9.4  Serial Peripheral Interface (SPI) Module
        1. 6.9.4.1 SPI Master Mode Electrical Data/Timing
          1. Table 6-37 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 6-38 SPI Master Mode External Timing (Clock Phase = 1)
        2. 6.9.4.2 SPI Slave Mode Electrical Data/Timing
          1. Table 6-39 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 6-40 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 6.9.5  Serial Communications Interface (SCI) Module
      6. 6.9.6  Local Interconnect Network (LIN)
      7. 6.9.7  Enhanced Controller Area Network (eCAN) Module
      8. 6.9.8  Inter-Integrated Circuit (I2C)
        1. 6.9.8.1 I2C Electrical Data/Timing
          1. Table 6-46 I2C Timing Requirements
          2. Table 6-47 I2C Switching Characteristics
      9. 6.9.9  Enhanced PWM Modules (ePWM1/2/3/4/5/6/7)
        1. 6.9.9.1 ePWM Electrical Data/Timing
          1. Table 6-50 ePWM Timing Requirements
          2. Table 6-51 ePWM Switching Characteristics
        2. 6.9.9.2 Trip-Zone Input Timing
          1. Table 6-52 Trip-Zone Input Timing Requirements
      10. 6.9.10 High-Resolution PWM (HRPWM)
        1. 6.9.10.1 HRPWM Electrical Data/Timing
          1. Table 6-53 High-Resolution PWM Characteristics
      11. 6.9.11 Enhanced Capture Module (eCAP1)
        1. 6.9.11.1 eCAP Electrical Data/Timing
          1. Table 6-55 Enhanced Capture (eCAP) Timing Requirement
          2. Table 6-56 eCAP Switching Characteristics
      12. 6.9.12 High-Resolution Capture (HRCAP) Module
        1. 6.9.12.1 HRCAP Electrical Data/Timing
          1. Table 6-58 High-Resolution Capture (HRCAP) Timing Requirements
      13. 6.9.13 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.9.13.1 eQEP Electrical Data/Timing
          1. Table 6-60 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
          2. Table 6-61 eQEP Switching Characteristics
      14. 6.9.14 JTAG Port
      15. 6.9.15 General-Purpose Input/Output (GPIO) MUX
        1. 6.9.15.1 GPIO Electrical Data/Timing
          1. 6.9.15.1.1 GPIO - Output Timing
            1. Table 6-67 General-Purpose Output Switching Characteristics
          2. 6.9.15.1.2 GPIO - Input Timing
            1. Table 6-68 General-Purpose Input Timing Requirements
          3. 6.9.15.1.3 Sampling Window Width for Input Signals
          4. 6.9.15.1.4 Low-Power Mode Wakeup Timing
            1. Table 6-69 IDLE Mode Timing Requirements
            2. Table 6-70 IDLE Mode Switching Characteristics
            3. Table 6-71 STANDBY Mode Timing Requirements
            4. Table 6-72 STANDBY Mode Switching Characteristics
            5. Table 6-73 HALT Mode Timing Requirements
            6. Table 6-74 HALT Mode Switching Characteristics
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device and Development Support Tool Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Description

C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-loop performance in real-time control applications such as industrial motor drives; solar inverters and digital power; electrical vehicles and transportation; motor control; and sensing and signal processing. The C2000 line includes the Delfino™ Premium Performance family and the Piccolo™ Entry Performance family.

The F2803x Piccolo™ family of microcontrollers provides the power of the C28x core and Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration.

An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency.

To learn more about the C2000 MCUs, visit the C2000 Overview at www.ti.com/c2000.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE
TMS320F28035PN LQFP (80) 12.0 mm × 12.0 mm
TMS320F28034PN LQFP (80) 12.0 mm × 12.0 mm
TMS320F28033PN LQFP (80) 12.0 mm × 12.0 mm
TMS320F28032PN LQFP (80) 12.0 mm × 12.0 mm
TMS320F28031PN LQFP (80) 12.0 mm × 12.0 mm
TMS320F28030PN LQFP (80) 12.0 mm × 12.0 mm
TMS320F28035PAG TQFP (64) 10.0 mm × 10.0 mm
TMS320F28034PAG TQFP (64) 10.0 mm × 10.0 mm
TMS320F28033PAG TQFP (64) 10.0 mm × 10.0 mm
TMS320F28032PAG TQFP (64) 10.0 mm × 10.0 mm
TMS320F28031PAG TQFP (64) 10.0 mm × 10.0 mm
TMS320F28030PAG TQFP (64) 10.0 mm × 10.0 mm
TMS320F28035RSH VQFN (56) 7.0 mm × 7.0 mm
TMS320F28034RSH VQFN (56) 7.0 mm × 7.0 mm
TMS320F28033RSH VQFN (56) 7.0 mm × 7.0 mm
TMS320F28032RSH VQFN (56) 7.0 mm × 7.0 mm
TMS320F28031RSH VQFN (56) 7.0 mm × 7.0 mm
TMS320F28030RSH VQFN (56) 7.0 mm × 7.0 mm
For more information on these devices, see Mechanical, Packaging, and Orderable Information.