SPRS797C November   2012  – October 2018 TMS320F28050 , TMS320F28051 , TMS320F28052 , TMS320F28053 , TMS320F28054 , TMS320F28055

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
      1. Table 5-1 TMS320F2805x Current Consumption at 60-MHz SYSCLKOUT
      2. 5.4.1     Reducing Current Consumption
      3. 5.4.2     Current Consumption Graphs (VREG Enabled)
    5. 5.5  Electrical Characteristics
    6. 5.6  Thermal Resistance Characteristics for PN Package
    7. 5.7  Thermal Design Considerations
    8. 5.8  Emulator Connection Without Signal Buffering for the MCU
    9. 5.9  Parameter Information
      1. 5.9.1 Timing Parameter Symbology
      2. 5.9.2 General Notes on Timing Parameters
    10. 5.10 Test Load Circuit
    11. 5.11 Power Sequencing
      1. Table 5-3 Reset (XRS) Timing Requirements
      2. Table 5-4 Reset (XRS) Switching Characteristics
    12. 5.12 Clock Specifications
      1. 5.12.1 Device Clock Table
        1. Table 5-5 2805x Clock Table and Nomenclature (60-MHz Devices)
        2. Table 5-6 Device Clocking Requirements/Characteristics
        3. Table 5-7 Internal Zero-Pin Oscillator (INTOSC1, INTOSC2) Characteristics
      2. 5.12.2 Clock Requirements and Characteristics
        1. Table 5-8  XCLKIN Timing Requirements - PLL Enabled
        2. Table 5-9  XCLKIN Timing Requirements - PLL Disabled
        3. Table 5-10 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    13. 5.13 Flash Timing
      1. Table 5-11 Flash/OTP Endurance for T Temperature Material
      2. Table 5-12 Flash/OTP Endurance for S Temperature Material
      3. Table 5-13 Flash/OTP Endurance for Q Temperature Material
      4. Table 5-14 Flash Parameters at 60-MHz SYSCLKOUT
      5. Table 5-15 Flash/OTP Access Timing
      6. Table 5-16 Flash Data Retention Duration
  6. 6Detailed Description
    1. 6.1 Overview
      1. 6.1.1  CPU
      2. 6.1.2  Control Law Accelerator
      3. 6.1.3  Memory Bus (Harvard Bus Architecture)
      4. 6.1.4  Peripheral Bus
      5. 6.1.5  Real-Time JTAG and Analysis
      6. 6.1.6  Flash
      7. 6.1.7  M0, M1 SARAMs
      8. 6.1.8  L0 SARAM, and L1, L2, and L3 DPSARAMs
      9. 6.1.9  Boot ROM
        1. 6.1.9.1 Emulation Boot
        2. 6.1.9.2 GetMode
        3. 6.1.9.3 Peripheral Pins Used by the Bootloader
      10. 6.1.10 Security
      11. 6.1.11 Peripheral Interrupt Expansion Block
      12. 6.1.12 External Interrupts (XINT1 to XINT3)
      13. 6.1.13 Internal Zero-Pin Oscillators, Oscillator, and PLL
      14. 6.1.14 Watchdog
      15. 6.1.15 Peripheral Clocking
      16. 6.1.16 Low-power Modes
      17. 6.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 6.1.18 General-Purpose Input/Output Multiplexer
      19. 6.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 6.1.20 Control Peripherals
      21. 6.1.21 Serial Port Peripherals
    2. 6.2 Memory Maps
    3. 6.3 Register Map
    4. 6.4 Device Emulation Registers
    5. 6.5 VREG, BOR, POR
      1. 6.5.1 On-chip VREG
        1. 6.5.1.1 Using the On-chip VREG
        2. 6.5.1.2 Disabling the On-chip VREG
      2. 6.5.2 On-chip Power-On Reset and Brownout Reset Circuit
    6. 6.6 System Control
      1. 6.6.1 Internal Zero-Pin Oscillators
      2. 6.6.2 Crystal Oscillator Option
      3. 6.6.3 PLL-Based Clock Module
      4. 6.6.4 Loss of Input Clock (NMI-watchdog Function)
      5. 6.6.5 CPU-watchdog Module
    7. 6.7 Low-power Modes Block
    8. 6.8 Interrupts
      1. 6.8.1 External Interrupts
        1. 6.8.1.1 External Interrupt Electrical Data/Timing
          1. Table 6-26 External Interrupt Timing Requirements
          2. Table 6-27 External Interrupt Switching Characteristics
    9. 6.9 Peripherals
      1. 6.9.1  Control Law Accelerator
        1. 6.9.1.1 CLA Device-Specific Information
        2. 6.9.1.2 CLA Register Descriptions
      2. 6.9.2  Analog Block
        1. 6.9.2.1 Analog-to-Digital Converter
          1. 6.9.2.1.1 ADC Device-Specific Information
          2. 6.9.2.1.2 ADC Electrical Data/Timing
            1. Table 6-32  ADC Electrical Characteristics
            2. Table 6-34  ADC Power Modes
            3. 6.9.2.1.2.1 External ADC Start-of-Conversion Electrical Data/Timing
              1. Table 6-35 External ADC Start-of-Conversion Switching Characteristics
            4. 6.9.2.1.2.2 Internal Temperature Sensor
              1. Table 6-36 Temperature Sensor Coefficient
            5. 6.9.2.1.2.3 ADC Power-Up Control Bit Timing
              1. Table 6-37 ADC Power-Up Delays
            6. 6.9.2.1.2.4 ADC Sequential and Simultaneous Timings
        2. 6.9.2.2 Analog Front End
          1. 6.9.2.2.1 AFE Device-Specific Information
          2. 6.9.2.2.2 AFE Register Descriptions
          3. 6.9.2.2.3 PGA Electrical Data/Timing
          4. 6.9.2.2.4 Comparator Block Electrical Data/Timing
            1. Table 6-45 Electrical Characteristics of the Comparator/DAC
          5. 6.9.2.2.5 VREFOUT Buffered DAC Electrical Data
            1. Table 6-46 Electrical Characteristics of VREFOUT Buffered DAC
      3. 6.9.3  Detailed Descriptions
      4. 6.9.4  Serial Peripheral Interface
        1. 6.9.4.1 SPI Device-Specific Information
        2. 6.9.4.2 SPI Register Descriptions
        3. 6.9.4.3 SPI Master Mode Electrical Data/Timing
          1. Table 6-48 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 6-49 SPI Master Mode External Timing (Clock Phase = 1)
        4. 6.9.4.4 SPI Slave Mode Electrical Data/Timing
          1. Table 6-50 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 6-51 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 6.9.5  Serial Communications Interface
        1. 6.9.5.1 SCI Device-Specific Information
        2. 6.9.5.2 SCI Register Descriptions
      6. 6.9.6  Enhanced Controller Area Network
        1. 6.9.6.1 eCAN Device-Specific Information
        2. 6.9.6.2 eCAN Register Descriptions
      7. 6.9.7  Inter-Integrated Circuit
        1. 6.9.7.1 I2C Device-Specific Information
        2. 6.9.7.2 I2C Register Descriptions
        3. 6.9.7.3 I2C Electrical Data/Timing
          1. Table 6-58 I2C Timing Requirements
          2. Table 6-59 I2C Switching Characteristics
      8. 6.9.8  Enhanced Pulse Width Modulator
        1. 6.9.8.1 ePWM Device-Specific Information
        2. 6.9.8.2 ePWM Register Descriptions
        3. 6.9.8.3 ePWM Electrical Data/Timing
          1. Table 6-62 ePWM Timing Requirements
          2. Table 6-63 ePWM Switching Characteristics
          3. 6.9.8.3.1  Trip-Zone Input Timing
            1. Table 6-64 Trip-Zone Input Timing Requirements
      9. 6.9.9  Enhanced Capture Module
        1. 6.9.9.1 eCAP Module Device-Specific Information
        2. 6.9.9.2 eCAP Module Register Descriptions
        3. 6.9.9.3 eCAP Module Electrical Data/Timing
          1. Table 6-66 eCAP Timing Requirement
          2. Table 6-67 eCAP Switching Characteristics
      10. 6.9.10 Enhanced Quadrature Encoder Pulse
        1. 6.9.10.1 eQEP Device-Specific Information
        2. 6.9.10.2 eQEP Register Descriptions
        3. 6.9.10.3 eQEP Electrical Data/Timing
          1. Table 6-69 eQEP Timing Requirements
          2. Table 6-70 eQEP Switching Characteristics
      11. 6.9.11 JTAG Port
        1. 6.9.11.1 JTAG Port Device-Specific Information
      12. 6.9.12 General-Purpose Input/Output
        1. 6.9.12.1 GPIO Device-Specific Information
        2. 6.9.12.2 GPIO Register Descriptions
        3. 6.9.12.3 GPIO Electrical Data/Timing
          1. 6.9.12.3.1 GPIO - Output Timing
            1. Table 6-74 General-Purpose Output Switching Characteristics
          2. 6.9.12.3.2 GPIO - Input Timing
            1. Table 6-75 General-Purpose Input Timing Requirements
          3. 6.9.12.3.3 Sampling Window Width for Input Signals
          4. 6.9.12.3.4 Low-Power Mode Wakeup Timing
            1. Table 6-76 IDLE Mode Timing Requirements
            2. Table 6-77 IDLE Mode Switching Characteristics
            3. Table 6-78 STANDBY Mode Timing Requirements
            4. Table 6-79 STANDBY Mode Switching Characteristics
            5. Table 6-80 HALT Mode Timing Requirements
            6. Table 6-81 HALT Mode Switching Characteristics
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device and Development Support Tool Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

ePWM Register Descriptions

Table 6-60 and Table 6-61 show the complete ePWM register set per module.

Table 6-60 ePWM1–ePWM4 Control and Status Registers

NAME ePWM1 ePWM2 ePWM3 ePWM4 SIZE (×16) / #SHADOW DESCRIPTION
TBCTL 0x6800 0x6840 0x6880 0x68C0 1 / 0 Time Base Control register
TBSTS 0x6801 0x6841 0x6881 0x68C1 1 / 0 Time Base Status register
Reserved 0x6802 0x6842 0x6882 0x68C2 1 / 0 Reserved
TBPHS 0x6803 0x6843 0x6883 0x68C3 1 / 0 Time Base Phase register
TBCTR 0x6804 0x6844 0x6884 0x68C4 1 / 0 Time Base Counter register
TBPRD 0x6805 0x6845 0x6885 0x68C5 1 / 1 Time Base Period Register Set
Reserved 0x6806 0x6846 0x6886 0x68C6 1 / 1 Reserved
CMPCTL 0x6807 0x6847 0x6887 0x68C7 1 / 0 Counter Compare Control register
Reserved 0x6808 0x6848 0x6888 0x68C8 1 / 1 Reserved
CMPA 0x6809 0x6849 0x6889 0x68C9 1 / 1 Counter Compare A Register Set
CMPB 0x680A 0x684A 0x688A 0x68CA 1 / 1 Counter Compare B Register Set
AQCTLA 0x680B 0x684B 0x688B 0x68CB 1 / 0 Action Qualifier Control register for output A
AQCTLB 0x680C 0x684C 0x688C 0x68CC 1 / 0 Action Qualifier Control register for output B
AQSFRC 0x680D 0x684D 0x688D 0x68CD 1 / 0 Action Qualifier Software Force register
AQCSFRC 0x680E 0x684E 0x688E 0x68CE 1 / 1 Action Qualifier Continuous S/W Force Register Set
DBCTL 0x680F 0x684F 0x688F 0x68CF 1 / 1 Dead-Band Generator Control register
DBRED 0x6810 0x6850 0x6890 0x68D0 1 / 0 Dead-Band Generator Rising Edge Delay Count register
DBFED 0x6811 0x6851 0x6891 0x68D1 1 / 0 Dead-Band Generator Falling Edge Delay Count register
TZSEL 0x6812 0x6852 0x6892 0x68D2 1 / 0 Trip Zone Select register(1)
TZDCSEL 0x6813 0x6853 0x6893 0x98D3 1 / 0 Trip Zone Digital Compare register
TZCTL 0x6814 0x6854 0x6894 0x68D4 1 / 0 Trip Zone Control register(1)
TZEINT 0x6815 0x6855 0x6895 0x68D5 1 / 0 Trip Zone Enable Interrupt register(1)
TZFLG 0x6816 0x6856 0x6896 0x68D6 1 / 0 Trip Zone Flag register (1)
TZCLR 0x6817 0x6857 0x6897 0x68D7 1 / 0 Trip Zone Clear register(1)
TZFRC 0x6818 0x6858 0x6898 0x68D8 1 / 0 Trip Zone Force register(1)
ETSEL 0x6819 0x6859 0x6899 0x68D9 1 / 0 Event Trigger Selection register
ETPS 0x681A 0x685A 0x689A 0x68DA 1 / 0 Event Trigger Prescale register
ETFLG 0x681B 0x685B 0x689B 0x68DB 1 / 0 Event Trigger Flag register
ETCLR 0x681C 0x685C 0x689C 0x68DC 1 / 0 Event Trigger Clear register
ETFRC 0x681D 0x685D 0x689D 0x68DD 1 / 0 Event Trigger Force register
PCCTL 0x681E 0x685E 0x689E 0x68DE 1 / 0 PWM Chopper Control register
Reserved 0x6820 0x6860 0x68A0 0x68E0 1 / 0 Reserved
Reserved 0x6821 - - - 1 / 0 Reserved
Reserved 0x6826 - - - 1 / 0 Reserved
Reserved 0x6828 0x6868 0x68A8 0x68E8 1 / 0 Reserved
Reserved 0x682A 0x686A 0x68AA 0x68EA 1 / W(2) Reserved
TBPRDM 0x682B 0x686B 0x68AB 0x68EB 1 / W(2) Time Base Period Register Mirror
Reserved 0x682C 0x686C 0x68AC 0x68EC 1 / W(2) Reserved
CMPAM 0x682D 0x686D 0x68AD 0x68ED 1 / W(2) Compare A Register Mirror
DCTRIPSEL 0x6830 0x6870 0x68B0 0x68F0 1 / 0 Digital Compare Trip Select register (1)
DCACTL 0x6831 0x6871 0x68B1 0x68F1 1 / 0 Digital Compare A Control register(1)
DCBCTL 0x6832 0x6872 0x68B2 0x68F2 1 / 0 Digital Compare B Control register(1)
DCFCTL 0x6833 0x6873 0x68B3 0x68F3 1 / 0 Digital Compare Filter Control register(1)
DCCAPCT 0x6834 0x6874 0x68B4 0x68F4 1 / 0 Digital Compare Capture Control register(1)
DCFOFFSET 0x6835 0x6875 0x68B5 0x68F5 1 / 1 Digital Compare Filter Offset register
DCFOFFSETCNT 0x6836 0x6876 0x68B6 0x68F6 1 / 0 Digital Compare Filter Offset Counter register
DCFWINDOW 0x6837 0x6877 0x68B7 0x68F7 1 / 0 Digital Compare Filter Window register
DCFWINDOWCNT 0x6838 0x6878 0x68B8 0x68F8 1 / 0 Digital Compare Filter Window Counter register
DCCAP 0x6839 0x6879 0x68B9 0x68F9 1 / 1 Digital Compare Counter Capture register
Registers that are EALLOW protected.
W = Write to shadow register

Table 6-61 ePWM5–ePWM7 Control and Status Registers

NAME ePWM5 ePWM6 ePWM7 SIZE (×16) / #SHADOW DESCRIPTION
TBCTL 0x6900 0x6940 0x6980 1 / 0 Time Base Control register
TBSTS 0x6901 0x6941 0x6981 1 / 0 Time Base Status register
Reserved 0x6902 0x6942 0x6982 1 / 0 Reserved
TBPHS 0x6903 0x6943 0x6983 1 / 0 Time Base Phase register
TBCTR 0x6904 0x6944 0x6984 1 / 0 Time Base Counter register
TBPRD 0x6905 0x6945 0x6985 1 / 1 Time Base Period Register Set
Reserved 0x6906 0x6946 0x6986 1 / 1 Reserved
CMPCTL 0x6907 0x6947 0x6987 1 / 0 Counter Compare Control register
Reserved 0x6908 0x6948 0x6988 1 / 1 Reserved
CMPA 0x6909 0x6949 0x6989 1 / 1 Counter Compare A Register Set
CMPB 0x690A 0x694A 0x698A 1 / 1 Counter Compare B Register Set
AQCTLA 0x690B 0x694B 0x698B 1 / 0 Action Qualifier Control register for output A
AQCTLB 0x690C 0x694C 0x698C 1 / 0 Action Qualifier Control register for output B
AQSFRC 0x690D 0x694D 0x698D 1 / 0 Action Qualifier Software Force register
AQCSFRC 0x690E 0x694E 0x698E 1 / 1 Action Qualifier Continuous S/W Force Register Set
DBCTL 0x690F 0x694F 0x698F 1 / 1 Dead-Band Generator Control register
DBRED 0x6910 0x6950 0x6990 1 / 0 Dead-Band Generator Rising Edge Delay Count register
DBFED 0x6911 0x6951 0x6991 1 / 0 Dead-Band Generator Falling Edge Delay Count register
TZSEL 0x6912 0x6952 0x6992 1 / 0 Trip Zone Select register(1)
TZDCSEL 0x6913 0x6953 0x6993 1 / 0 Trip Zone Digital Compare register
TZCTL 0x6914 0x6954 0x6994 1 / 0 Trip Zone Control register(1)
TZEINT 0x6915 0x6955 0x6995 1 / 0 Trip Zone Enable Interrupt register(1)
TZFLG 0x6916 0x6956 0x6996 1 / 0 Trip Zone Flag register (1)
TZCLR 0x6917 0x6957 0x6997 1 / 0 Trip Zone Clear register(1)
TZFRC 0x6918 0x6958 0x6998 1 / 0 Trip Zone Force register(1)
ETSEL 0x6919 0x6959 0x6999 1 / 0 Event Trigger Selection register
ETPS 0x691A 0x695A 0x699A 1 / 0 Event Trigger Prescale register
ETFLG 0x691B 0x695B 0x699B 1 / 0 Event Trigger Flag register
ETCLR 0x691C 0x695C 0x699C 1 / 0 Event Trigger Clear register
ETFRC 0x691D 0x695D 0x699D 1 / 0 Event Trigger Force register
PCCTL 0x691E 0x695E 0x699E 1 / 0 PWM Chopper Control register
Reserved 0x6920 0x6960 0x69A0 1 / 0 Reserved
Reserved - - - 1 / 0 Reserved
Reserved - - - 1 / 0 Reserved
Reserved 0x6928 0x6968 0x69A8 1 / 0 Reserved
Reserved 0x692A 0x696A 0x69AA 1 / W(2) Reserved
TBPRDM 0x692B 0x696B 0x69AB 1 / W(2) Time Base Period Register Mirror
Reserved 0x692C 0x696C 0x69AC 1 / W(2) Reserved
CMPAM 0x692D 0x696D 0x69AD 1 / W(2) Compare A Register Mirror
DCTRIPSEL 0x6930 0x6970 0x69B0 1 / 0 Digital Compare Trip Select register (1)
DCACTL 0x6931 0x6971 0x69B1 1 / 0 Digital Compare A Control register(1)
DCBCTL 0x6932 0x6972 0x69B2 1 / 0 Digital Compare B Control register(1)
DCFCTL 0x6933 0x6973 0x69B3 1 / 0 Digital Compare Filter Control register(1)
DCCAPCT 0x6934 0x6974 0x69B4 1 / 0 Digital Compare Capture Control register(1)
DCFOFFSET 0x6935 0x6975 0x69B5 1 / 1 Digital Compare Filter Offset register
DCFOFFSETCNT 0x6936 0x6976 0x69B6 1 / 0 Digital Compare Filter Offset Counter register
DCFWINDOW 0x6937 0x6977 0x69B7 1 / 0 Digital Compare Filter Window register
DCFWINDOWCNT 0x6938 0x6978 0x69B8 1 / 0 Digital Compare Filter Window Counter register
DCCAP 0x6939 0x6979 0x69B9 1 / 1 Digital Compare Counter Capture register
Registers that are EALLOW protected.
W = Write to shadow register