SPRS797C November   2012  – October 2018 TMS320F28050 , TMS320F28051 , TMS320F28052 , TMS320F28053 , TMS320F28054 , TMS320F28055

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
      1. Table 5-1 TMS320F2805x Current Consumption at 60-MHz SYSCLKOUT
      2. 5.4.1     Reducing Current Consumption
      3. 5.4.2     Current Consumption Graphs (VREG Enabled)
    5. 5.5  Electrical Characteristics
    6. 5.6  Thermal Resistance Characteristics for PN Package
    7. 5.7  Thermal Design Considerations
    8. 5.8  Emulator Connection Without Signal Buffering for the MCU
    9. 5.9  Parameter Information
      1. 5.9.1 Timing Parameter Symbology
      2. 5.9.2 General Notes on Timing Parameters
    10. 5.10 Test Load Circuit
    11. 5.11 Power Sequencing
      1. Table 5-3 Reset (XRS) Timing Requirements
      2. Table 5-4 Reset (XRS) Switching Characteristics
    12. 5.12 Clock Specifications
      1. 5.12.1 Device Clock Table
        1. Table 5-5 2805x Clock Table and Nomenclature (60-MHz Devices)
        2. Table 5-6 Device Clocking Requirements/Characteristics
        3. Table 5-7 Internal Zero-Pin Oscillator (INTOSC1, INTOSC2) Characteristics
      2. 5.12.2 Clock Requirements and Characteristics
        1. Table 5-8  XCLKIN Timing Requirements - PLL Enabled
        2. Table 5-9  XCLKIN Timing Requirements - PLL Disabled
        3. Table 5-10 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    13. 5.13 Flash Timing
      1. Table 5-11 Flash/OTP Endurance for T Temperature Material
      2. Table 5-12 Flash/OTP Endurance for S Temperature Material
      3. Table 5-13 Flash/OTP Endurance for Q Temperature Material
      4. Table 5-14 Flash Parameters at 60-MHz SYSCLKOUT
      5. Table 5-15 Flash/OTP Access Timing
      6. Table 5-16 Flash Data Retention Duration
  6. 6Detailed Description
    1. 6.1 Overview
      1. 6.1.1  CPU
      2. 6.1.2  Control Law Accelerator
      3. 6.1.3  Memory Bus (Harvard Bus Architecture)
      4. 6.1.4  Peripheral Bus
      5. 6.1.5  Real-Time JTAG and Analysis
      6. 6.1.6  Flash
      7. 6.1.7  M0, M1 SARAMs
      8. 6.1.8  L0 SARAM, and L1, L2, and L3 DPSARAMs
      9. 6.1.9  Boot ROM
        1. 6.1.9.1 Emulation Boot
        2. 6.1.9.2 GetMode
        3. 6.1.9.3 Peripheral Pins Used by the Bootloader
      10. 6.1.10 Security
      11. 6.1.11 Peripheral Interrupt Expansion Block
      12. 6.1.12 External Interrupts (XINT1 to XINT3)
      13. 6.1.13 Internal Zero-Pin Oscillators, Oscillator, and PLL
      14. 6.1.14 Watchdog
      15. 6.1.15 Peripheral Clocking
      16. 6.1.16 Low-power Modes
      17. 6.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 6.1.18 General-Purpose Input/Output Multiplexer
      19. 6.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 6.1.20 Control Peripherals
      21. 6.1.21 Serial Port Peripherals
    2. 6.2 Memory Maps
    3. 6.3 Register Map
    4. 6.4 Device Emulation Registers
    5. 6.5 VREG, BOR, POR
      1. 6.5.1 On-chip VREG
        1. 6.5.1.1 Using the On-chip VREG
        2. 6.5.1.2 Disabling the On-chip VREG
      2. 6.5.2 On-chip Power-On Reset and Brownout Reset Circuit
    6. 6.6 System Control
      1. 6.6.1 Internal Zero-Pin Oscillators
      2. 6.6.2 Crystal Oscillator Option
      3. 6.6.3 PLL-Based Clock Module
      4. 6.6.4 Loss of Input Clock (NMI-watchdog Function)
      5. 6.6.5 CPU-watchdog Module
    7. 6.7 Low-power Modes Block
    8. 6.8 Interrupts
      1. 6.8.1 External Interrupts
        1. 6.8.1.1 External Interrupt Electrical Data/Timing
          1. Table 6-26 External Interrupt Timing Requirements
          2. Table 6-27 External Interrupt Switching Characteristics
    9. 6.9 Peripherals
      1. 6.9.1  Control Law Accelerator
        1. 6.9.1.1 CLA Device-Specific Information
        2. 6.9.1.2 CLA Register Descriptions
      2. 6.9.2  Analog Block
        1. 6.9.2.1 Analog-to-Digital Converter
          1. 6.9.2.1.1 ADC Device-Specific Information
          2. 6.9.2.1.2 ADC Electrical Data/Timing
            1. Table 6-32  ADC Electrical Characteristics
            2. Table 6-34  ADC Power Modes
            3. 6.9.2.1.2.1 External ADC Start-of-Conversion Electrical Data/Timing
              1. Table 6-35 External ADC Start-of-Conversion Switching Characteristics
            4. 6.9.2.1.2.2 Internal Temperature Sensor
              1. Table 6-36 Temperature Sensor Coefficient
            5. 6.9.2.1.2.3 ADC Power-Up Control Bit Timing
              1. Table 6-37 ADC Power-Up Delays
            6. 6.9.2.1.2.4 ADC Sequential and Simultaneous Timings
        2. 6.9.2.2 Analog Front End
          1. 6.9.2.2.1 AFE Device-Specific Information
          2. 6.9.2.2.2 AFE Register Descriptions
          3. 6.9.2.2.3 PGA Electrical Data/Timing
          4. 6.9.2.2.4 Comparator Block Electrical Data/Timing
            1. Table 6-45 Electrical Characteristics of the Comparator/DAC
          5. 6.9.2.2.5 VREFOUT Buffered DAC Electrical Data
            1. Table 6-46 Electrical Characteristics of VREFOUT Buffered DAC
      3. 6.9.3  Detailed Descriptions
      4. 6.9.4  Serial Peripheral Interface
        1. 6.9.4.1 SPI Device-Specific Information
        2. 6.9.4.2 SPI Register Descriptions
        3. 6.9.4.3 SPI Master Mode Electrical Data/Timing
          1. Table 6-48 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 6-49 SPI Master Mode External Timing (Clock Phase = 1)
        4. 6.9.4.4 SPI Slave Mode Electrical Data/Timing
          1. Table 6-50 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 6-51 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 6.9.5  Serial Communications Interface
        1. 6.9.5.1 SCI Device-Specific Information
        2. 6.9.5.2 SCI Register Descriptions
      6. 6.9.6  Enhanced Controller Area Network
        1. 6.9.6.1 eCAN Device-Specific Information
        2. 6.9.6.2 eCAN Register Descriptions
      7. 6.9.7  Inter-Integrated Circuit
        1. 6.9.7.1 I2C Device-Specific Information
        2. 6.9.7.2 I2C Register Descriptions
        3. 6.9.7.3 I2C Electrical Data/Timing
          1. Table 6-58 I2C Timing Requirements
          2. Table 6-59 I2C Switching Characteristics
      8. 6.9.8  Enhanced Pulse Width Modulator
        1. 6.9.8.1 ePWM Device-Specific Information
        2. 6.9.8.2 ePWM Register Descriptions
        3. 6.9.8.3 ePWM Electrical Data/Timing
          1. Table 6-62 ePWM Timing Requirements
          2. Table 6-63 ePWM Switching Characteristics
          3. 6.9.8.3.1  Trip-Zone Input Timing
            1. Table 6-64 Trip-Zone Input Timing Requirements
      9. 6.9.9  Enhanced Capture Module
        1. 6.9.9.1 eCAP Module Device-Specific Information
        2. 6.9.9.2 eCAP Module Register Descriptions
        3. 6.9.9.3 eCAP Module Electrical Data/Timing
          1. Table 6-66 eCAP Timing Requirement
          2. Table 6-67 eCAP Switching Characteristics
      10. 6.9.10 Enhanced Quadrature Encoder Pulse
        1. 6.9.10.1 eQEP Device-Specific Information
        2. 6.9.10.2 eQEP Register Descriptions
        3. 6.9.10.3 eQEP Electrical Data/Timing
          1. Table 6-69 eQEP Timing Requirements
          2. Table 6-70 eQEP Switching Characteristics
      11. 6.9.11 JTAG Port
        1. 6.9.11.1 JTAG Port Device-Specific Information
      12. 6.9.12 General-Purpose Input/Output
        1. 6.9.12.1 GPIO Device-Specific Information
        2. 6.9.12.2 GPIO Register Descriptions
        3. 6.9.12.3 GPIO Electrical Data/Timing
          1. 6.9.12.3.1 GPIO - Output Timing
            1. Table 6-74 General-Purpose Output Switching Characteristics
          2. 6.9.12.3.2 GPIO - Input Timing
            1. Table 6-75 General-Purpose Input Timing Requirements
          3. 6.9.12.3.3 Sampling Window Width for Input Signals
          4. 6.9.12.3.4 Low-Power Mode Wakeup Timing
            1. Table 6-76 IDLE Mode Timing Requirements
            2. Table 6-77 IDLE Mode Switching Characteristics
            3. Table 6-78 STANDBY Mode Timing Requirements
            4. Table 6-79 STANDBY Mode Switching Characteristics
            5. Table 6-80 HALT Mode Timing Requirements
            6. Table 6-81 HALT Mode Switching Characteristics
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device and Development Support Tool Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

GPIO Register Descriptions

The device supports 42 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 6-73 provides the GPIO register mapping.

Table 6-73 GPIO Registers

NAME ADDRESS SIZE (×16) DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL 0x6F80 2 GPIO A Control register (GPIO0 to 31)
GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 register (GPIO0 to 15)
GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 register (GPIO16 to 31)
GPAMUX1 0x6F86 2 GPIO A MUX 1 register (GPIO0 to 15)
GPAMUX2 0x6F88 2 GPIO A MUX 2 register (GPIO16 to 31)
GPADIR 0x6F8A 2 GPIO A Direction register (GPIO0 to 31)
GPAPUD 0x6F8C 2 GPIO A Pull Up Disable register (GPIO0 to 31)
GPBCTRL 0x6F90 2 GPIO B Control register (GPIO32 to 44)
GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 register (GPIO32 to 44)
GPBMUX1 0x6F96 2 GPIO B MUX 1 register (GPIO32 to 44)
GPBDIR 0x6F9A 2 GPIO B Direction register (GPIO32 to 44)
GPBPUD 0x6F9C 2 GPIO B Pull Up Disable register (GPIO32 to 44)
Reserved 0x6FB6 2 Reserved
Reserved 0x6FBA 2 Reserved
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT 0x6FC0 2 GPIO A Data register (GPIO0 to 31)
GPASET 0x6FC2 2 GPIO A Data Set register (GPIO0 to 31)
GPACLEAR 0x6FC4 2 GPIO A Data Clear register (GPIO0 to 31)
GPATOGGLE 0x6FC6 2 GPIO A Data Toggle register (GPIO0 to 31)
GPBDAT 0x6FC8 2 GPIO B Data register (GPIO32 to 44)
GPBSET 0x6FCA 2 GPIO B Data Set register (GPIO32 to 44)
GPBCLEAR 0x6FCC 2 GPIO B Data Clear register (GPIO32 to 44)
GPBTOGGLE 0x6FCE 2 GPIO B Data Toggle register (GPIO32 to 44)
Reserved 0x6FD8 2 Reserved
Reserved 0x6FDA 2 Reserved
Reserved 0x6FDC 2 Reserved
Reserved 0x6FDE 2 Reserved
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select register (GPIO0 to 31)
GPIOXINT2SEL 0x6FE1 1 XINT2 GPIO Input Select register (GPIO0 to 31)
GPIOXINT3SEL 0x6FE2 1 XINT3 GPIO Input Select register (GPIO0 to 31)
GPIOLPMSEL 0x6FE8 2 LPM GPIO Select register (GPIO0 to 31)

NOTE

There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn and GPxQSELn registers occurs to when the action is valid.