SPRSP14 May   2019 TMS320F28384D , TMS320F28384S , TMS320F28386D , TMS320F28386S , TMS320F28388D , TMS320F28388S

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1 Analog Signals
      2. 4.3.2 Digital Signals
      3. 4.3.3 Power and Ground
      4. 4.3.4 Test, JTAG, and Reset
    4. 4.4 Pins With Internal Pullup and Pulldown
    5. 4.5 Pin Multiplexing
      1. 4.5.1 GPIO Muxed Pins
      2. 4.5.2 Input X-BAR
      3. 4.5.3 Output X-BAR and ePWM X-BAR
      4. 4.5.4 USB Pin Muxing
      5. 4.5.5 High-Speed SPI Pin Muxing
      6. 4.5.6 High-Speed SSI Pin Muxing
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 System Current Consumption (External Supply)
      2. 5.5.1     Operating Mode Test Description
      3. 5.5.2     Reducing Current Consumption
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 ZWT Package
      2. 5.7.2 Thermal Design Considerations
    8. 5.8  System
      1. 5.8.1 Power Sequencing
      2. 5.8.2 Reset Timing
        1. 5.8.2.1 Reset Sources
        2. 5.8.2.2 Reset Electrical Data and Timing
          1. Table 5-3 Reset (XRSn) Timing Requirements
          2. Table 5-4 Reset (XRSn) Switching Characteristics
      3. 5.8.3 Clock Specifications
        1. 5.8.3.1 Clock Sources
        2. 5.8.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 5.8.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. Table 5-6  Input Clock Frequency
            2. Table 5-7  X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
            3. Table 5-8  XTAL Oscillator Characteristics
            4. Table 5-9  X1 Timing Requirements
            5. Table 5-10 AUXCLKIN Timing Requirements
            6. Table 5-11 APLL Characteristics
          2. 5.8.3.2.2 Internal Clock Frequencies
            1. Table 5-12 Internal Clock Frequencies
          3. 5.8.3.2.3 Output Clock Frequency and Switching Characteristics
            1. Table 5-13 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        3. 5.8.3.3 Input Clocks
        4. 5.8.3.4 Crystal Oscillator
          1. Table 5-14 Crystal Oscillator Parameters
          2. Table 5-16 Crystal Oscillator Electrical Characteristics
        5. 5.8.3.5 Internal Oscillators
          1. Table 5-17 INTOSC Characteristics
      4. 5.8.4 Flash Parameters
      5. 5.8.5 Emulation/JTAG
        1. 5.8.5.1 JTAG Electrical Data and Timing
          1. Table 5-19 JTAG Timing Requirements
          2. Table 5-20 JTAG Switching Characteristics
      6. 5.8.6 GPIO Electrical Data and Timing
        1. 5.8.6.1 GPIO - Output Timing
          1. Table 5-21 General-Purpose Output Switching Characteristics
        2. 5.8.6.2 GPIO - Input Timing
          1. Table 5-22 General-Purpose Input Timing Requirements
        3. 5.8.6.3 Sampling Window Width for Input Signals
      7. 5.8.7 Interrupts
        1. 5.8.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. Table 5-23 External Interrupt Timing Requirements
          2. Table 5-24 External Interrupt Switching Characteristics
      8. 5.8.8 Low-Power Modes
        1. 5.8.8.1 Clock-Gating Low-Power Modes
        2. 5.8.8.2 Low-Power Mode Wakeup Timing
          1. Table 5-26 IDLE Mode Timing Requirements
          2. Table 5-27 IDLE Mode Switching Characteristics
          3. Table 5-28 STANDBY Mode Timing Requirements
          4. Table 5-29 STANDBY Mode Switching Characteristics
      9. 5.8.9 External Memory Interface (EMIF)
        1. 5.8.9.1 Asynchronous Memory Support
        2. 5.8.9.2 Synchronous DRAM Support
        3. 5.8.9.3 EMIF Electrical Data and Timing
          1. 5.8.9.3.1 Asynchronous RAM
            1. Table 5-30 EMIF Asynchronous Memory Timing Requirements
            2. Table 5-31 EMIF Asynchronous Memory Switching Characteristics
          2. 5.8.9.3.2 Synchronous RAM
            1. Table 5-32 EMIF Synchronous Memory Timing Requirements
            2. Table 5-33 EMIF Synchronous Memory Switching Characteristics
    9. 5.9  C28x Analog Peripherals
      1. 5.9.1 Analog Subsystem
      2. 5.9.2 Analog-to-Digital Converter (ADC)
        1. 5.9.2.1 ADC Configurability
          1. 5.9.2.1.1 Signal Mode
        2. 5.9.2.2 ADC Electrical Data and Timing
          1. Table 5-35 ADC Operating Conditions (16-bit Differential)
          2. Table 5-36 ADC Characteristics (16-bit Differential)
          3. Table 5-37 ADC Operating Conditions (16-bit Single-Ended)
          4. Table 5-38 ADC Characteristics (16-bit Single-Ended)
          5. Table 5-39 ADC Operating Conditions (12-bit Single-Ended)
          6. Table 5-40 ADC Characteristics (12-bit Single-Ended)
          7. Table 5-41 ADCEXTSOC Timing Requirements
          8. 5.9.2.2.1  ADC Input Models
            1. Table 5-42 Single-Ended Input Model Parameters (12-bit Resolution)
            2. Table 5-43 Single-Ended Input Model Parameters (16-bit Resolution)
            3. Table 5-44 Differential Input Model Parameters (16-bit Resolution)
          9. 5.9.2.2.2  ADC Timing Diagrams
            1. Table 5-47 ADC Timings in 12-Bit Mode (SYSCLK Cycles)
            2. Table 5-48 ADC Timings in 16-Bit Mode
        3. 5.9.2.3 Temperature Sensor Electrical Data and Timing
          1. Table 5-49 Temperature Sensor Characteristics
      3. 5.9.3 Comparator Subsystem (CMPSS)
        1. 5.9.3.1 CMPSS Electrical Data and Timing
          1. Table 5-50 Comparator Electrical Characteristics
          2. Table 5-51 CMPSS DAC Static Electrical Characteristics
      4. 5.9.4 Buffered Digital-to-Analog Converter (DAC)
        1. 5.9.4.1 Buffered DAC Electrical Data and Timing
          1. Table 5-52 Buffered DAC Operating Conditions
          2. Table 5-53 Buffered DAC Electrical Characteristics
    10. 5.10 C28x Control Peripherals
      1. 5.10.1 Enhanced Capture and High-Resolution Capture (eCAP, HRCAP)
        1. 5.10.1.1 eCAP Synchronization
        2. 5.10.1.2 eCAP Electrical Data and Timing
          1. Table 5-54 eCAP Timing Requirements
          2. Table 5-55 eCAP Switching Charcteristics
        3. 5.10.1.3 HRCAP Electrical Data and Timing
          1. Table 5-56 HRCAP Switching Characteristics
      2. 5.10.2 Enhanced Pulse Width Modulator (ePWM)
        1. 5.10.2.1 Control Peripherals Synchronization
        2. 5.10.2.2 ePWM Electrical Data and Timing
          1. Table 5-57 ePWM Timing Requirements
          2. Table 5-58 ePWM Switching Characteristics
          3. 5.10.2.2.1 Trip-Zone Input Timing
            1. Table 5-59 Trip-Zone Input Timing Requirements
        3. 5.10.2.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. Table 5-60 External ADC Start-of-Conversion Switching Characteristics
      3. 5.10.3 High-Resolution Pulse Width Modulator (HRPWM)
        1. 5.10.3.1 HRPWM Electrical Data and Timing
          1. Table 5-61 High-Resolution PWM Characteristics
      4. 5.10.4 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 5.10.4.1 eQEP Electrical Data and Timing
          1. Table 5-62 eQEP Timing Requirements
          2. Table 5-63 eQEP Switching Characteristics
      5. 5.10.5 Sigma-Delta Filter Module (SDFM)
        1. 5.10.5.1 SDFM Electrical Data and Timing (Using ASYNC)
          1. Table 5-64 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
    11. 5.11 C28x Communications Peripherals
      1. 5.11.1 Controller Area Network (CAN)
      2. 5.11.2 Fast Serial Interface (FSI)
        1. 5.11.2.1 FSI Transmitter
          1. 5.11.2.1.1 FSITX Electrical Data and Timing
            1. Table 5-65 FSITX Switching Characteristics
        2. 5.11.2.2 FSI Receiver
          1. 5.11.2.2.1 FSIRX Electrical Data and Timing
            1. Table 5-66 FSIRX Timing Requirements
        3. 5.11.2.3 SPI Signaling Mode
          1. 5.11.2.3.1 FSITX SPI Mode Electrical Data and Timing
            1. Table 5-67 FSITX SPI Mode Switching Characteristics
      3. 5.11.3 Inter-Integrated Circuit (I2C)
        1. 5.11.3.1 I2C Electrical Data and Timing
          1. Table 5-68 I2C Timing Requirements
          2. Table 5-69 I2C Switching Characteristics
      4. 5.11.4 Multichannel Buffered Serial Port (McBSP)
        1. 5.11.4.1 McBSP Electrical Data and Timing
          1. 5.11.4.1.1 McBSP Transmit and Receive Timing
            1. Table 5-70 McBSP Timing Requirements
            2. Table 5-71 McBSP Switching Characteristics
          2. 5.11.4.1.2 McBSP as SPI Master or Slave Timing
            1. Table 5-72 McBSP as SPI Master Timing Requirements
            2. Table 5-73 McBSP as SPI Master Switching Characteristics
            3. Table 5-74 McBSP as SPI Slave Timing Requirements
            4. Table 5-75 McBSP as SPI Slave Switching Characteristics
      5. 5.11.5 Power Management Bus (PMBus)
        1. 5.11.5.1 PMBus Electrical Data and Timing
          1. Table 5-76 PMBus Electrical Characteristics
          2. Table 5-77 PMBus Fast Mode Switching Characteristics
          3. Table 5-78 PMBus Standard Mode Switching Characteristics
      6. 5.11.6 Serial Communications Interface (SCI)
      7. 5.11.7 Serial Peripheral Interface (SPI)
        1. 5.11.7.1 SPI Electrical Data and Timing
          1. 5.11.7.1.1 SPI Master Mode Timings
            1. Table 5-79 SPI Master Mode Timing Requirements
            2. Table 5-80 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            3. Table 5-81 SPI Master Mode Switching Characteristics (Clock Phase = 1)
          2. 5.11.7.1.2 SPI Slave Mode Timings
            1. Table 5-82 SPI Slave Mode Timing Requirements
            2. Table 5-83 SPI Slave Mode Switching Characteristics
      8. 5.11.8 EtherCAT Slave Controller (ESC)
        1. 5.11.8.1 ESC Features
        2. 5.11.8.2 ESC Subsystem Integrated Features
        3. 5.11.8.3 EtherCAT IP Block Diagram
        4. 5.11.8.4 EtherCAT Electrical Data and Timing
          1. Table 5-84 EtherCAT Timing Requirements
          2. Table 5-85 EtherCAT Switching Characteristics
      9. 5.11.9 Universal Serial Bus (USB) Controller
        1. 5.11.9.1 USB Electrical Data and Timing
          1. Table 5-86 USB Input Ports DP and DM Timing Requirements
          2. Table 5-87 USB Output Ports DP and DM Switching Characteristics
    12. 5.12 Connectivity Manager (CM) Peripherals
      1. 5.12.1 Modular Controller Area Network (MCAN) [CAN FD]
      2. 5.12.2 Ethernet Media Access Controller (EMAC)
        1. 5.12.2.1 MAC Features
          1. 5.12.2.1.1 MAC Tx and Rx Features
          2. 5.12.2.1.2 MAC Tx Features
          3. 5.12.2.1.3 MAC Rx Features
        2. 5.12.2.2 Ethernet Electrical Data and Timing
          1. Table 5-88 Ethernet Timing Requirements
          2. Table 5-89 Ethernet Switching Characteristics
        3. 5.12.2.3 Ethernet REVMII Electrical Data and Timing
          1. Table 5-90 Ethernet REVMII Timing Requirements
          2. Table 5-91 Ethernet REVMII Switching Characteristics
      3. 5.12.3 Inter-Integrated Circuit (CM-I2C)
        1. 5.12.3.1 CM-I2C Electrical Data and Timing
          1. Table 5-92 CM-I2C Timing Requirements
          2. Table 5-93 CM-I2C Switching Characteristics
      4. 5.12.4 Synchronous Serial Interface (SSI)
        1. 5.12.4.1 SSI Electrical Data and Timing
          1. Table 5-94 SSI Timing Requirements
          2. Table 5-95 SSI Characteristics
      5. 5.12.5 Universal Asynchronous Receiver/Transmitter (CM-UART)
      6. 5.12.6 Trace Port Interface Unit (TPIU)
        1. 5.12.6.1 TPIU Electrical Data and Timing
          1. Table 5-97 Trace Port Switching Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Memory
      1. 6.3.1 C28x Memory Map
      2. 6.3.2 C28x Flash Memory Map
      3. 6.3.3 EMIF Chip Select Memory Map
      4. 6.3.4 CM Memory Map
      5. 6.3.5 CM Flash Memory Map
      6. 6.3.6 Memory Types
        1. 6.3.6.1 Dedicated RAM (Mx and Dx RAM)
        2. 6.3.6.2 Local Shared RAM (LSx RAM)
        3. 6.3.6.3 Global Shared RAM (GSx RAM)
        4. 6.3.6.4 CPU Message RAM (CPU MSGRAM)
        5. 6.3.6.5 CLA Message RAM (CLA MSGRAM)
        6. 6.3.6.6 CLA - DMA Message RAM (CLA-DMA MSGRAM)
        7. 6.3.6.7 CPUx - CM Message RAM (CPUx-CM MSGRAM)
        8. 6.3.6.8 Dedicated RAM (C0/C1 RAM)
        9. 6.3.6.9 Shared RAM (E0 and Sx RAM)
    4. 6.4 Identification
    5. 6.5 Bus Architecture – Peripheral Connectivity
    6. 6.6 Boot ROM and Peripheral Booting
      1. 6.6.1 Device Boot
      2. 6.6.2 Device Boot Modes
      3. 6.6.3 Device Boot Configurations
      4. 6.6.4 GPIO Assignments for CPU1
    7. 6.7 Dual Code Security Module (DCSM)
    8. 6.8 C28x (CPU1/CPU2) Subsystem
      1. 6.8.1  C28x Processor
        1. 6.8.1.1 Floating-Point Unit
        2. 6.8.1.2 Trigonometric Math Unit
        3. 6.8.1.3 Fast Integer Division Accelerator
        4. 6.8.1.4 VCRC Unit
      2. 6.8.2  Embedded Real-Time Analysis and Diagnostic (ERAD)
      3. 6.8.3  Background CRC-32 (BGCRC)
      4. 6.8.4  Control Law Accelerator (CLA)
      5. 6.8.5  Direct Memory Access (DMA)
      6. 6.8.6  Interprocessor Communication (IPC) Module
      7. 6.8.7  C28x Timers
      8. 6.8.8  Dual-Clock Comparator (DCC)
        1. 6.8.8.1 Features
        2. 6.8.8.2 Mapping of DCCx (DCC0, DCC1, and DCC2) Clock Source Inputs
      9. 6.8.9  Nonmaskable Interrupt With Watchdog Timer (NMIWD)
      10. 6.8.10 Watchdog
      11. 6.8.11 Configurable Logic Block (CLB)
    9. 6.9 Connectivity Manager (CM) Subsystem
      1. 6.9.1  Arm Cortex-M4 Processor
      2. 6.9.2  Nested Vectored Interrupt Controller (NVIC)
      3. 6.9.3  Advance Encryption Standard (AES) Accelerator
      4. 6.9.4  Generic Cyclic Redundancy Check (GCRC) Module
      5. 6.9.5  CM Nonmaskable Interrupt (CMNMI) Module
      6. 6.9.6  Memory Protection Unit (MPU)
      7. 6.9.7  Micro Direct Memory Access (µDMA)
      8. 6.9.8  Watchdog
      9. 6.9.9  CM Clocking
        1. 6.9.9.1 CM Clock Sources
      10. 6.9.10 CM Timers
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Markings
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZWT|337
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device Overview