SLLSE96F September   2011  – October 2015 TPD12S016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4  Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Conforms to HDMI Compliance Tests Without any External Components
      2. 7.3.2  IEC 61000-4-2 ESD Protection
      3. 7.3.3  Supports HDMI 1.4 Data Rate
      4. 7.3.4  Matches Class D and Class C Pin Mapping
      5. 7.3.5  8-Channel ESD Lines for Four Differential Pairs with Ultra-low Differential Capacitance Matching (0.05 pF)
      6. 7.3.6  On-Chip Load Switch With 55-mA Current Limit Feature at the HDMI 5V_OUT Pin
      7. 7.3.7  Auto-direction Sensing I2C Level Shifter With One-Shot Circuit to Drive a Long HDMI Cable (750-pF Load)
      8. 7.3.8  Back-Drive Protection on HDMI Connector Side Ports
      9. 7.3.9  Integrated Pullup and Pulldown Resistors per HDMI Specification
      10. 7.3.10 Space Saving 24-Pin RKT Package and 24-TSSOP Package
      11. 7.3.11 DDC/CEC LEVEL SHIFT Circuit Operation
      12. 7.3.12 DDC/CEC Level Shifter Operational Notes For VCCA = 1.8 V
      13. 7.3.13 Rise-Time Accelerators
      14. 7.3.14 Noise Considerations
      15. 7.3.15 Resistor Pullup Value Selection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Example 1: HDMI Controller Using One Control Line
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Example 2: HDMI Controller Using CT_HPD and LS_OE
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 TPD12S016RKT
      2. 10.2.2 TPD12S016PW
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RKT|24
  • PW|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

  • The optimum placement is as close to the connector as possible.
    • EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. Therefore, the PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector.
  • Route the protected traces as straight as possible.
  • Avoid using VIAs between the connecter and an I/O protection pin on TPD12S016.
  • Avoid 90º turns in traces.
    • Electric fields tend to build up on corners, increasing EMI coupling.
  • Minimize impedance on the path to GND for maximum ESD dissipation.
  • The capacitors on VBUS and VOTG_IN should be placed close to their respective pins on TPD12S016.

10.2 Layout Examples

10.2.1 TPD12S016RKT

TPD12S016 SLLSE96_Layout_RKT.gif Figure 19. TPD12S016RKT Layout Example

Routing with TPD12S016RKT requires three layers. Vias are an integral part of layout for such a design. Proper placement of vias can eliminate exposing the system unnecessarily to an ESD event. The example shown above routes the TMDS lines directly from the connector to the protection pins before using vias to an internal layer. This helps promote ESD energy dissipation at the TPD12S016 protection pins. Note that while there is a via between the connector and the DDC/CEC/HPD lines, the traces terminate at the protection pins, leaving no other path for ESD energy to dissipate except at the TPD12S016 protection pins. All ground pins should have a large via near them connecting to as many internal and external ground planes as possible to reduce any impedance between TPD12S016 and ground. Tenting of VIAs near to SMD pads should be done to eliminate any solder-wicking during PCB assembly.

10.2.2 TPD12S016PW

TPD12S016 SLLSE96_Layout_PW.gif Figure 20. TPD12S016PW Layout Example

The TPD12S016PW can be routed on a single layer. HDMI connector pin matching has been arranged to allow for a flow through routing style. All ground pins should have a large via near them connecting to as many internal and external ground planes as possible to reduce any impedance between TPD12S016 and ground. Tenting of vias near to SMD pads should be done to eliminate any solder-wicking during PCB assembly.