SLVS953B June   2009  – August 2015 TPD2E009

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

Layout considerations such as package selection, trace routing, and so forth, must be accounted for while designing the ESD clamp circuit for a high-speed interface. Difficult routing can lead the designer to use vias or stubs in the board traces, which creates significant disruption in the line impedance in the high-speed signal path. Poor package choice can force the designer to route differential traces with unequal lengths and add the skew in the signals. TI recommends coupling the differential traces closely to reduce the EMI interference.

The TPD2E009 can provide system-level ESD protection to the high-speed differential ports (up to 6-Gbps data rate). The flow-through package offers flexibility for board routing with traces up to 15 mils (0.38 mm) wide. Figure 14 and Figure 15 show the board layout scheme for the D+ and D– lines of a single differential pair, which allows the differential signal pairs to couple together right after they touch the ESD ports (pin 1 and pin 2) of the TPD2E009.

10.2 Layout Examples

TPD2E009 esata_drt_lvs953.gifFigure 14. TPD2E009DRTR at eSATA Connector Interface
TPD2E009 esata_dbz_lvs953.gifFigure 15. TPD2E009DBZR at eSATA Connector Interface