SLVSB01D October   2011  – August 2016 TPS54295

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation
      2. 7.3.2 PWM Frequency and Adaptive On-Time Control
      3. 7.3.3 Auto-Skip Eco-Mode Control
      4. 7.3.4 Soft Start and Prebiased Soft Start
      5. 7.3.5 Overcurrent Protection
      6. 7.3.6 Overvoltage and Undervoltage Protection
      7. 7.3.7 UVLO Protection
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Eco-Mode Operation
      3. 7.4.3 Standby Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Resistors Selection
        2. 8.2.2.2 Output Filter Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Bootstrap Capacitor Selection
        5. 8.2.2.5 VREG5 Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

  1. Keep the input current loop as small as possible. And avoid the input switching current through the thermal pad.
  2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions.
  3. Keep analog and non-switching components away from switching components.
  4. Make a single point connection from the signal ground to power ground.
  5. Do not allow switching currents to flow under the device.
  6. Keep the pattern lines for VINx and PGNDx broad.
  7. Exposed pad of device must be soldered to PGND.
  8. VREG5 capacitor must be placed near the device, and connected to GND.
  9. Output capacitors must be connected with a broad pattern to the PGND.
  10. Voltage feedback loops must be as short as possible, and preferably with ground shields.
  11. Kelvin connections must be brought from the output to the feedback pin of the device.
  12. Providing sufficient vias is preferable for VIN, SW, and PGND connections.
  13. PCB pattern for VIN, SW, and PGND must be as broad as possible.
  14. VIN capacitor must be placed as near as possible to the device.

10.2 Layout Example

TPS54295 layout_lvsb01.gif Figure 25. TPS54295 PWP Package Layout
TPS54295 RSA_Layout_54295_new_lvsb01.gif Figure 26. TPS54295 RSA Package Layout

10.3 Thermal Considerations

This 16-pin PWP package incorporates an exposed thermal pad. The thermal pad must be soldered directly to the printed-circuit board (PCB). After soldering, the PCB is used as a heat sink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heat sink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC).

For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating abilities, see PowerPAD Thermally Enhanced Package and PowerPAD Made Easy.

The exposed thermal pad dimensions for this package are shown in Figure 27.

TPS54295 therm_pad_lvsb01.gif Figure 27. Thermal Pad Dimensions