SLUSE15 February   2020 TPS546B24A

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Average Current-Mode Control
        1. 7.3.1.1 On-Time Modulator
        2. 7.3.1.2 Current Error Integrator
        3. 7.3.1.3 Voltage Error Integrator
      2. 7.3.2  Linear Regulators
      3. 7.3.3  AVIN and PVIN Pins
      4. 7.3.4  Input Undervoltage Lockout (UVLO)
        1. 7.3.4.1 Fixed AVIN UVLO
        2. 7.3.4.2 Fixed VDD5 UVLO
        3. 7.3.4.3 Programmable PVIN UVLO
        4. 7.3.4.4 EN/UVLO Pin
      5. 7.3.5  Start-Up and Shutdown
      6. 7.3.6  Differential Sense Amplifier and Feedback Divider
      7. 7.3.7  Set Output Voltage and Adaptive Voltage Scaling (AVS)
        1. 7.3.7.1 Reset Output Voltage
        2. 7.3.7.2 Soft Start
      8. 7.3.8  Prebiased Output Start-Up
      9. 7.3.9  Soft Stop and Command
      10. 7.3.10 7.3.10 Power Good (PGOOD)
      11. 7.3.11 Set Switching Frequency
      12. 7.3.12 Frequency Synchronization
      13. 7.3.13 Loop Slave Detection
      14. 7.3.14 Current Sensing and Sharing
      15. 7.3.15 Telemetry
      16. 7.3.16 Overcurrent Protection
      17. 7.3.17 Overvoltage/Undervoltage Protection
      18. 7.3.18 Overtemperature Management
      19. 7.3.19 Fault Management
      20. 7.3.20 Back-Channel communication
      21. 7.3.21 Switching Node (SW)
      22. 7.3.22 PMBus General Description
      23. 7.3.23 PMBus Address
      24. 7.3.24 PMBus Connections
    4. 7.4 Device Functional Modes
      1. 7.4.1 Programming Mode
      2. 7.4.2 StandAlone/Master/Slave Mode Pin Connections
      3. 7.4.3 Continuous Conduction Mode
      4. 7.4.4 Operation With CNTL Signal Control
      5. 7.4.5 Operation with Control
      6. 7.4.6 Operation with CNTL and Control
    5. 7.5 Programming
      1. 7.5.1 Supported PMBus Commands
      2. 7.5.2 Pin Strapping
        1. 7.5.2.1 Programming MSEL1
        2. 7.5.2.2 Programming MSEL2
        3. 7.5.2.3 Programming VSEL
        4. 7.5.2.4 Programming ADRSEL
        5. 7.5.2.5 Programming MSEL2 for a Slave Device (GOSNS tied to BP1V5)
        6. 7.5.2.6 Pin-Strapping Resistor Configuration
    6. 7.6 Register Maps
      1. 7.6.1  Conventions for Documenting Block Commands
      2. 7.6.2  (01h) OPERATION
        1. Table 19. Register Field Descriptions
      3. 7.6.3  (02h) ON_OFF_CONFIG
        1. Table 20. Register Field Descriptions
      4. 7.6.4  (03h) CLEAR_FAULTS
      5. 7.6.5  (04h) PHASE
        1. Table 21. Register Field Descriptions
      6. 7.6.6  (10h) WRITE_PROTECT
        1. Table 22. Register Field Descriptions
      7. 7.6.7  (15h) STORE_USER_ALL
      8. 7.6.8  (16h) RESTORE_USER_ALL
      9. 7.6.9  (19h) CAPABILITY
        1. Table 23. Register Field Descriptions
      10. 7.6.10 (1Bh) SMBALERT_MASK
      11. 7.6.11 (1Bh) SMBALERT_MASK_VOUT
        1. Table 24. Register Field Descriptions
      12. 7.6.12 (1Bh) SMBALERT_MASK_IOUT
        1. Table 25. Register Field Descriptions
      13. 7.6.13 (1Bh) SMBALERT_MASK_INPUT
        1. Table 26. Register Field Descriptions
      14. 7.6.14 (1Bh) SMBALERT_MASK_TEMPERATURE
        1. Table 27. Register Field Descriptions
      15. 7.6.15 (1Bh) SMBALERT_MASK_CML
        1. Table 28. Register Field Descriptions
      16. 7.6.16 (1Bh) SMBALERT_MASK_OTHER
        1. Table 29. Register Field Descriptions
      17. 7.6.17 (1Bh) SMBALERT_MASK_MFR
        1. Table 30. Register Field Descriptions
      18. 7.6.18 (20h) VOUT_MODE
        1. Table 31. Register Field Descriptions
      19. 7.6.19 (21h) VOUT_COMMAND
        1. Table 32. Register Field Descriptions
      20. 7.6.20 (22h) VOUT_TRIM
        1. Table 33. Register Field Descriptions
      21. 7.6.21 (24h) VOUT_MAX
        1. Table 35. Register Field Descriptions
      22. 7.6.22 (25h) VOUT_MARGIN_HIGH
        1. Table 36. Register Field Descriptions
      23. 7.6.23 (26h) VOUT_MARGIN_LOW
        1. Table 37. Register Field Descriptions
      24. 7.6.24 (27h) VOUT_TRANSITION_RATE
        1. Table 38. Register Field Descriptions
      25. 7.6.25 (29h) VOUT_SCALE_LOOP
        1. Table 39. Register Field Descriptions
      26. 7.6.26 (2Bh) VOUT_MIN
        1. Table 41. Register Field Descriptions
      27. 7.6.27 (33h) FREQUENCY_SWITCH
        1. Table 42. Register Field Descriptions
      28. 7.6.28 (35h) VIN_ON
        1. Table 44. Register Field Descriptions
      29. 7.6.29 (36h) VIN_OFF
        1. Table 45. Register Field Descriptions
      30. 7.6.30 (37h) INTERLEAVE
        1. Table 46. Register Field Descriptions
      31. 7.6.31 (38h) IOUT_CAL_GAIN
        1. Table 48. Register Field Descriptions
      32. 7.6.32 (39h) IOUT_CAL_OFFSET
        1. Table 49. Register Field Descriptions
      33. 7.6.33 (40h) VOUT_OV_FAULT_LIMIT
        1. Table 50. Register Field Descriptions
      34. 7.6.34 (41h) VOUT_OV_FAULT_RESPONSE
        1. Table 51. Register Field Descriptions
      35. 7.6.35 (42h) VOUT_OV_WARN_LIMIT
        1. Table 52. Register Field Descriptions
      36. 7.6.36 (43h) VOUT_UV_WARN_LIMIT
        1. Table 53. Register Field Descriptions
      37. 7.6.37 (44h) VOUT_UV_FAULT_LIMIT
        1. Table 54. Register Field Descriptions
      38. 7.6.38 (45h) VOUT_UV_FAULT_RESPONSE
        1. Table 55. Register Field Descriptions
      39. 7.6.39 (46h) IOUT_OC_FAULT_LIMIT
        1. Table 56. Register Field Descriptions
      40. 7.6.40 (47h) IOUT_OC_FAULT_RESPONSE
        1. Table 57. Register Field Descriptions
      41. 7.6.41 (4Ah) IOUT_OC_WARN_LIMIT
        1. Table 58. Register Field Descriptions
      42. 7.6.42 (4Fh) OT_FAULT_LIMIT
        1. Table 59. Register Field Descriptions
      43. 7.6.43 (50h) OT_FAULT_RESPONSE
        1. Table 60. Register Field Descriptions
      44. 7.6.44 (51h) OT_WARN_LIMIT
        1. Table 61. Register Field Descriptions
      45. 7.6.45 (55h) VIN_OV_FAULT_LIMIT
        1. Table 62. Register Field Descriptions
      46. 7.6.46 (56h) VIN_OV_FAULT_RESPONSE
        1. Table 63. Register Field Descriptions
      47. 7.6.47 (58h) VIN_UV_WARN_LIMIT
        1. Table 64. Register Field Descriptions
      48. 7.6.48 (60h) TON_DELAY
        1. Table 65. Register Field Descriptions
      49. 7.6.49 (61h) TON_RISE
        1. Table 66. Register Field Descriptions
      50. 7.6.50 (62h) TON_MAX_FAULT_LIMIT
        1. Table 67. Register Field Descriptions
      51. 7.6.51 (63h) TON_MAX_FAULT_RESPONSE
        1. Table 68. Register Field Descriptions
      52. 7.6.52 (64h) TOFF_DELAY
        1. Table 69. Register Field Descriptions
      53. 7.6.53 (65h) TOFF_FALL
        1. Table 70. Register Field Descriptions
      54. 7.6.54 (78h) STATUS_BYTE
        1. Table 71. Register Field Descriptions
      55. 7.6.55 (79h) STATUS_WORD
        1. Table 72. Register Field Descriptions
      56. 7.6.56 (7Ah) STATUS_VOUT
        1. Table 73. Register Field Descriptions
      57. 7.6.57 (7Bh) STATUS_IOUT
        1. Table 74. Register Field Descriptions
      58. 7.6.58 (7Ch) STATUS_INPUT
        1. Table 75. Register Field Descriptions
      59. 7.6.59 (7Dh) STATUS_TEMPERATURE
        1. Table 76. Register Field Descriptions
      60. 7.6.60 (7Eh) STATUS_CML
        1. Table 77. Register Field Descriptions
      61. 7.6.61 (7Fh) STATUS_OTHER
        1. Table 78. Register Field Descriptions
      62. 7.6.62 (80h) STATUS_MFR_SPECIFIC
        1. Table 79. Register Field Descriptions
      63. 7.6.63 (88h) READ_VIN
        1. Table 80. Register Field Descriptions
      64. 7.6.64 (8Bh) READ_VOUT
        1. Table 81. Register Field Descriptions
      65. 7.6.65 (8Ch) READ_IOUT
        1. Table 82. Register Field Descriptions
      66. 7.6.66 (8Dh) READ_TEMPERATURE_1
        1. Table 83. Register Field Descriptions
      67. 7.6.67 (98h) PMBUS_REVISION
        1. Table 84. Register Field Descriptions
      68. 7.6.68 (99h) MFR_ID
        1. Table 85. Register Field Descriptions
      69. 7.6.69 (9Ah) MFR_MODEL
        1. Table 86. Register Field Descriptions
      70. 7.6.70 (9Bh) MFR_REVISION
        1. Table 87. Register Field Descriptions
      71. 7.6.71 (9Eh) MFR_SERIAL
        1. Table 88. Register Field Descriptions
      72. 7.6.72 (ADh) IC_DEVICE_ID
        1. Table 89. Register Field Descriptions
      73. 7.6.73 (AEh) IC_DEVICE_REV
      74. 7.6.74 (B1h) USER_DATA_01 (COMPENSATION_CONFIG)
        1. Table 91. Register Field Descriptions
      75. 7.6.75 (B5h) USER_DATA_05 (POWER_STAGE_CONFIG)
        1. Table 92. Register Field Descriptions
      76. 7.6.76 (D0h) MFR_SPECIFIC_00 (TELEMETRY_CONFIG)
        1. Table 93. Register Field Descriptions
      77. 7.6.77 (DAh) MFR_SPECIFIC_10 (READ_ALL)
        1. Table 94. Register Field Descriptions
      78. 7.6.78 (DBh) MFR_SPECIFIC_11 (STATUS_ALL)
        1. Table 95. Register Field Descriptions
      79. 7.6.79 (DCh) MFR_SPECIFIC_12 (STATUS_PHASE)
        1. Table 96. Register Field Descriptions
      80. 7.6.80 (E4h) MFR_SPECIFIC_20 (SYNC_CONFIG)
        1. Table 97. Register Field Descriptions
      81. 7.6.81 (ECh) MFR_SPECIFIC_28 (STACK_CONFIG)
        1. Table 98. Register Field Descriptions
      82. 7.6.82 (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS)
        1. Table 99. Register Field Descriptions
      83. 7.6.83 (EEh) MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE)
        1. Table 100. Register Field Descriptions
      84. 7.6.84 (EFh) MFR_SPECIFIC_31 (SLAVE_ADDRESS)
        1. Table 101. Register Field Descriptions
      85. 7.6.85 (F0h) MFR_SPECIFIC_32 (NVM_CHECKSUM)
        1. Table 102. Register Field Descriptions
      86. 7.6.86 (F1h) MFR_SPECIFIC_33 (SIMULATE_FAULT)
        1. Table 103. Register Field Descriptions
      87. 7.6.87 (FCh) MFR_SPECIFIC_44 (FUSION_ID0)
        1. Table 104. Register Field Descriptions
      88. 7.6.88 (FDh) MFR_SPECIFIC_45 (FUSION_ID1)
        1. Table 105. Register Field Descriptions
  8. Power Supply Recommendations
  9. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Mounting and Thermal Profile Recommendation
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
        2. 10.1.2.2 Texas Instruments Fusion Digital Power Designer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • Split rail support: 2.95-V to 18-V PVIN;
    2.95-V to 18-V AVIN (4-VIN VDD5 for switching)
  • Integrated 5.5-mΩ/1.8-mΩ MOSFETs
  • Average current mode control with selectable internal compensation
  • 2×, 3x, 4× stackable with current sharing up to 80 A, supporting a single address per output
  • Selectable 0.6-V to 5.5-V output via pin strap or 0.25-V to 6.0-V using PMBus VOUT_COMMAND
  • Extensive PMBus command set with telemetry for VOUT, IOUT and internal die temperature
  • Differential remote sensing with internal FB divider for < 1% VOUT error –40°C to +150°C TJ
  • AVS and margining capabilities through PMBus
  • MSEL pins pin programming PMBus defaults
  • 12 Selectable switching frequencies from 225 kHz to 1.5 MHz (8 pin-strap options)
  • Frequency sync in/sync out
  • Supports prebiased output
  • Supports strongly coupled inductor
  • 7 mm × 5 mm × 1.5 mm, 40-pin QFN,
    Pitch = 0.5 mm
  • Create a Custom Design Using the TPS546B24A With WEBENCH® Power Designer