SLVSCQ5A December   2014  – February 2015 TPS62184

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable / Shutdown (EN)
      2. 8.3.2 Soft Start / Tracking (SS/TR)
      3. 8.3.3 Power Good (PG)
      4. 8.3.4 Undervoltage Lockout (UVLO)
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode (PSM) Operation
      3. 8.4.3 Minimum Duty Cycle and 100% Mode Operation
      4. 8.4.4 Automatic Efficiency Enhancement (AEE)
      5. 8.4.5 Phase-Shifted Operation
      6. 8.4.6 Current Limit, Current Balancing, and Short Circuit Protection
      7. 8.4.7 Tracking
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical TPS62184 Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Programming the Output Voltage
          2. 9.2.1.2.2 Output Filter Selection
          3. 9.2.1.2.3 Inductor Selection
          4. 9.2.1.2.4 Output Capacitor Selection
          5. 9.2.1.2.5 Input Capacitor Selection
          6. 9.2.1.2.6 Soft Start Capacitor Selection
          7. 9.2.1.2.7 Using the Accurate EN Threshold
        3. 9.2.1.3 Application Performance Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB layout
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

The PCB layout of the TPS62184 demands careful attention to ensure proper operation, thermal profile, low noise emission and to achieve best performance. A poor layout can lead to issues like poor regulation, stability and accuracy weaknesses, increased EMI radiation and noise sensitivity. While the TPS62184 provides very high power density, the PCB layout also contributes significantly to the thermal performance.

11.1.1 PCB layout

A recommended PCB layout for the TPS62184 dual phase solution is shown below. It ensures best electrical and optimized thermal performance considering the following important topics:

- The input capacitors must be placed as close as possible to the appropriate pins of the device. This provides low resistive and inductive paths for the high di/dt input current. The input capacitance is split, as is the VIN connection, to avoid interference between the input lines.

- The SW node connection from the IC to the inductor conducts high currents. It should be kept short and can be designed in parallel with an internal or bottom layer plane, to provide low resistance and enhanced thermal behavior.

- The VOUT regulation loop is closed with COUT and its ground connection. If a ground layer or plane is used, a direct connection by vias, as shown, is recommended. Otherwise the connection of COUT to GND must be short for good load regulation.

- The FB node is sensitive to dv/dt signals. Therefore the resistive divider should be placed close to the FB pin, avoiding long trace distance.

11.2 Layout Example

TPS62184 SLVSBB8_layout.gifFigure 39. TPS62184 Board Layout