SLVSCQ5A December   2014  – February 2015 TPS62184

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable / Shutdown (EN)
      2. 8.3.2 Soft Start / Tracking (SS/TR)
      3. 8.3.3 Power Good (PG)
      4. 8.3.4 Undervoltage Lockout (UVLO)
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode (PSM) Operation
      3. 8.4.3 Minimum Duty Cycle and 100% Mode Operation
      4. 8.4.4 Automatic Efficiency Enhancement (AEE)
      5. 8.4.5 Phase-Shifted Operation
      6. 8.4.6 Current Limit, Current Balancing, and Short Circuit Protection
      7. 8.4.7 Tracking
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical TPS62184 Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Programming the Output Voltage
          2. 9.2.1.2.2 Output Filter Selection
          3. 9.2.1.2.3 Inductor Selection
          4. 9.2.1.2.4 Output Capacitor Selection
          5. 9.2.1.2.5 Input Capacitor Selection
          6. 9.2.1.2.6 Soft Start Capacitor Selection
          7. 9.2.1.2.7 Using the Accurate EN Threshold
        3. 9.2.1.3 Application Performance Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB layout
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

24-Pin DSBGA
YZF Package
(Top View - Left, Bottom View - Right)
TPS62184 SLVSCQ5_pinout.gif

Pin Functions

PIN(1) DESCRIPTION
NAME NUMBER
AGND C4 Analog Ground. Connect on PCB directly with PGND.
EN E4 Enable input (High = enabled, Low = disabled)
FB B4 Output voltage feedback. Connect resistive voltage divider to this pin and AGND. On TPS62182, connect to AGND.
PG F4 Output power good (High = VOUT ready, Low = VOUT below nominal regulation); open drain (requires pull-up resistor)
PGND A3, B3, C3, D3, E3, F3 Common power ground.
SS/TR D4 Soft-Start and Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise time.
SW1 A2, B2, C2 Switch node for Phase 1 (master), connected to the internal MOSFET switches. Connect inductor 1 between SW1 and output capacitor.
SW2 D2, E2, F2 Switch node for Phase 2 (follower), connected to the internal MOSFET switches. Connect inductor 2 between SW2 and output capacitor.
VIN1 A1, B1, C1 Supply voltage for Phase 1.
VIN2 D1, E1, F1 Supply voltage for Phase 2.
VO A4 Output Voltage Connection
(1) For more information about connecting pins, see Detailed Description and Application Information sections.