SLVSDD1E December   2017  – January 2019 TPS62800 , TPS62801 , TPS62802 , TPS62806 , TPS62807 , TPS62808

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application
      2.      Efficiency vs. IOUT at 1.2VOUT
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Smart Enable and Shutdown (EN)
      2. 8.3.2 Softstart
      3. 8.3.3 VSEL/MODE Pin
        1. 8.3.3.1 Output Voltage Selection (R2D Converter)
        2. 8.3.3.2 Mode Selection: Power Save Mode / Forced PWM Operation
      4. 8.3.4 Undervoltage Lockout (UVLO)
      5. 8.3.5 Switch Current Limit / Short Circuit Protection
      6. 8.3.6 Thermal Shutdown
      7. 8.3.7 Output Voltage Discharge
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Save Mode Operation
      2. 8.4.2 Forced PWM Mode Operation
      3. 8.4.3 100% Mode Operation
      4. 8.4.4 Optimized Transient Performance from PWM to PFM Mode Operation
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Custom Design With WEBENCH® Tools
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

The pinout of TPS6280x has been optimized to enable a single top layer PCB routing of the IC and its critical passive components such as CIN, COUT and L. Furthermore, this pin out allows to connect tiny components such as 0201 (0603) size capacitors and 0402 (1005) size inductor. A solution size smaller than 5mm2 can be achieved with a fixed output voltage.

  • As for all switching power supplies, the layout is an important step in the design. Care must be taken in board layout to get the specified performance.
  • It is critical to provide a low inductance, low impedance ground path. Therefore, use wide and short traces for the main current paths.
  • The input capacitor should be placed as close as possible to the IC's VIN and GND pins. This is the most critical component placement.
  • The VOS line is a sensitive, high impedance line and should be connected to the output capacitor and routed away from noisy components and traces (e.g. SW line) or other noise sources.