SLVSB04A July   2011  – August 2015 TPS65186

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Data Transmission
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Wake-Up and Power-Up Sequencing
      2. 8.3.2  Dependencies Between Rails
      3. 8.3.3  Soft Start
      4. 8.3.4  VPOS/VNEG Supply Tracking
      5. 8.3.5  V3P3 Power Switch
      6. 8.3.6  VCOM Adjustment
        1. 8.3.6.1 Kick-Back Voltage Measurement
        2. 8.3.6.2 Storing the VCOM Power-Up Default Value in Memory
      7. 8.3.7  Fault Handling and Recovery
      8. 8.3.8  Power Good Pin
      9. 8.3.9  Interrupt Pin
      10. 8.3.10 Panel Temperature Monitoring
        1. 8.3.10.1 NTC Bias Circuit
        2. 8.3.10.2 Hot, Cold, and Temperature-Change Interrupts
        3. 8.3.10.3 Typical Application of the Temperature Monitor
    4. 8.4 Device Functional Modes
      1. 8.4.1 SLEEP
      2. 8.4.2 STANDBY
      3. 8.4.3 ACTIVE
      4. 8.4.4 Mode Transitions
        1. 8.4.4.1 SLEEP → ACTIVE
        2. 8.4.4.2 SLEEP → STANDBY
        3. 8.4.4.3 STANDBY → ACTIVE
        4. 8.4.4.4 ACTIVE → STANDBY
        5. 8.4.4.5 STANDBY → SLEEP
        6. 8.4.4.6 ACTIVE → SLEEP
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Operation
    6. 8.6 Register Maps
      1. 8.6.1  Thermistor Readout (TMST_VALUE)
      2. 8.6.2  Enable (ENABLE)
      3. 8.6.3  Voltage Adjustment Register (VADJ)
      4. 8.6.4  VCOM 1 (VCOM1)
      5. 8.6.5  VCOM 2 (VCOM2)
      6. 8.6.6  Interrupt Enable 1 (INT_EN1)
      7. 8.6.7  Interrupt Enable 2 (INT_EN2)
      8. 8.6.8  Interrupt 1 (INT1)
      9. 8.6.9  Interrupt 2 (INT2)
      10. 8.6.10 Power Up Sequence Register 0 (UPSEQ0)
      11. 8.6.11 Power Up Sequence Register 1 (UPSEQ1)
      12. 8.6.12 Power Down Sequence Register 0 (DWNSEQ0)
      13. 8.6.13 Power Down Sequence Register 1 (DWNSEQ1)
      14. 8.6.14 Thermistor Register 1 (TMST1)
      15. 8.6.15 Thermistor Register 2 (TMST2)
      16. 8.6.16 Power Good Status (PG)
      17. 8.6.17 Revision and Version Control (REVID)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Single Chip Power-Management Solution for
    E Ink®Vizplex™ Electronic Paper Displays
  • Generates Positive and Negative Gates, Source Driver Voltages, and Back-Plane Bias From a Single, Low-Voltage Input Supply
  • Supports 9.7 Inch and Larger Panel Size
  • 3-V to 6-V Input Voltage Range
  • Boost Converter for Positive Rail Base
  • Inverting Buck-Boost Converter for Negative Rail Base
  • Two Adjustable LDOs for Source Driver Supply
    • LDO1: 15 V, 120 mA (VPOS)
    • LDO2: –15 V, 120 mA (VNEG)
  • Accurate Output Voltage Tracking
    • VPOS – VNEG = ±50 mV
  • Two Charge Pumps for Gate Driver Supply
    • CP1: 22 V, 10 mA (VDDH)
    • CP2: –20 V, 12 mA, (VEE)
  • Adjustable VCOM Driver for Accurate Panel-Backplane Biasing
    • 0 V to –5.11 V
    • ± 1.5% accuracy (±10 mV)
    • 9-Bit Control (10-mV Nominal Step Size)
  • Integrated 10-Ω, 3.3-V Power Switch for Disabling System Power Rail to E-Ink Panel

2 Applications

  • Power Supply for Active Matrix E Ink Vizplex Panels
  • EPD Power Supplies
  • E-Book Readers
  • EPSON® S1D13522 (ISIS) Timing Controller
  • EPSON® S1D13521 (Broadsheet) Timing Controller
  • Application Processors With Integrated or Software Timing Controller (OMAP™)

3 Description

The TPS65186 device is a single-chip power supply designed to for E Ink Vizplex displays used in portable e-reader applications, and the device supports panel sizes up to 9.7 inches and greater. Two high-efficiency DC-DC boost converters generate ±16-V rails that are boosted to 22 V and –20 V by two change pumps to provide the gate driver supply for the Vizplex panel. Two tracking LDOs create the ±15-V source driver supplies that support up to 120-mA of output current. All rails are adjustable through the I2C interface to accommodate specific panel requirements.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS65186 VQFN (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Schematic

TPS65186 ces_slvsaq9.gif