SLIS165G December   2014  – February 2019 TPS659037

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Simplified Block Diagram
  2. 2 Revision History
  3. 3 Pin Configuration and Functions
    1.     Pin Functions
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: Latch Up Rating
    6. 4.6  Electrical Characteristics: LDO Regulator
    7. 4.7  Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase (SMPS123 and SMPS457) Regulators
    8. 4.8  Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9)
    9. 4.9  Electrical Characteristics: Reference Generator (Bandgap)
    10. 4.10 Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and Output Buffers
    11. 4.11 Electrical Characteristics: DC-DC Clock Sync
    12. 4.12 Electrical Characteristics: 12-Bit Sigma-Delta ADC
    13. 4.13 Electrical Characteristics: Thermal Monitoring and Shutdown
    14. 4.14 Electrical Characteristics: System Control Threshold
    15. 4.15 Electrical Characteristics: Current Consumption
    16. 4.16 Electrical Characteristics: Digital Input Signal Parameters
    17. 4.17 Electrical Characteristics: Digital Output Signal Parameters
    18. 4.18 Electrical Characteristics: I/O Pullup and Pulldown
    19. 4.19 I2C Interface Timing Requirements
    20. 4.20 SPI Timing Requirements
    21. 4.21 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1  Power Management
      2. 5.3.2  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
        1. 5.3.2.1 Step-Down Regulators
          1. 5.3.2.1.1 Sync Clock Functionality
          2. 5.3.2.1.2 Output Voltage and Mode Selection
          3. 5.3.2.1.3 Current Monitoring and Short Circuit Detection
          4. 5.3.2.1.4 POWERGOOD
          5. 5.3.2.1.5 DVS-Capable Regulators
          6. 5.3.2.1.6 Non DVS-Capable Regulators
          7. 5.3.2.1.7 Step-Down Converters SMPS12 and SMPS123
            1.         a. Dual-Phase SMPS and Stand-Alone SMPS
            2.         b. Triple Phase SMPS
          8. 5.3.2.1.8 Step-Down Converter SMPS45 and SMPS457
          9. 5.3.2.1.9 Step-Down Converters SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9
        2. 5.3.2.2 LDOs – Low Dropout Regulators
          1. 5.3.2.2.1 LDOVANA
          2. 5.3.2.2.2 LDOVRTC
          3. 5.3.2.2.3 LDO Bypass (LDO9)
          4. 5.3.2.2.4 LDOUSB
          5. 5.3.2.2.5 Other LDOs
      3. 5.3.3  Long-Press Key Detection
      4. 5.3.4  RTC
        1. 5.3.4.1 General Description
        2. 5.3.4.2 Time Calendar Registers
          1. 5.3.4.2.1 TC Registers Read Access
          2. 5.3.4.2.2 TC Registers Write Access
        3. 5.3.4.3 RTC Alarm
        4. 5.3.4.4 RTC Interrupts
        5. 5.3.4.5 RTC 32-kHz Oscillator Drift Compensation
      5. 5.3.5  GPADC – 12-Bit Sigma-Delta ADC
        1. 5.3.5.1 Asynchronous Conversion Request (SW)
        2. 5.3.5.2 Periodic Conversion Request (AUTO)
        3. 5.3.5.3 Calibration
      6. 5.3.6  General-Purpose I/Os (GPIO Pins)
        1. 5.3.6.1 REGEN Output
      7. 5.3.7  Thermal Monitoring
        1. 5.3.7.1 Hot-Die Function (HD)
        2. 5.3.7.2 Thermal Shutdown (TS)
        3. 5.3.7.3 Temperature Monitoring With External NTC Resistor or Diode
      8. 5.3.8  Interrupts
      9. 5.3.9  Control Interfaces
        1. 5.3.9.1 I2C Interfaces
          1. 5.3.9.1.1 I2C Implementation
          2. 5.3.9.1.2 F/S Mode Protocol
          3. 5.3.9.1.3 HS Mode Protocol
        2. 5.3.9.2 Serial-Peripheral Interface (SPI)
          1. 5.3.9.2.1 SPI Modes
          2. 5.3.9.2.2 SPI Protocol
      10. 5.3.10 Device Identification
    4. 5.4 Device Functional Modes
      1. 5.4.1  Embedded Power Controller
      2. 5.4.2  State Transition Requests
        1. 5.4.2.1 ON Requests
        2. 5.4.2.2 OFF Requests
        3. 5.4.2.3 SLEEP and WAKE Requests
      3. 5.4.3  Power Sequences
      4. 5.4.4  Startup Timing and RESET_OUT Generation
      5. 5.4.5  Power On Acknowledge
        1. 5.4.5.1 POWERHOLD Mode
        2. 5.4.5.2 AUTODEVON Mode
      6. 5.4.6  BOOT Configuration
        1. 5.4.6.1 Boot Pin Selection
      7. 5.4.7  Reset Levels
      8. 5.4.8  Warm Reset
      9. 5.4.9  RESET_IN
      10. 5.4.10 Watchdog Timer (WDT)
      11. 5.4.11 System Voltage Monitoring
        1. 5.4.11.1 Generating a POR
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1  Recommended External Components
        2. 6.2.2.2  SMPS Input Capacitors
        3. 6.2.2.3  SMPS Output Capacitors
        4. 6.2.2.4  SMPS Inductors
        5. 6.2.2.5  LDO Input Capacitors
        6. 6.2.2.6  LDO Output Capacitors
        7. 6.2.2.7  VCC1
          1. 6.2.2.7.1 Meeting the Power Down Sequence
          2. 6.2.2.7.2 Maintaining Sufficient Input Voltage
        8. 6.2.2.8  VIO_IN
        9. 6.2.2.9  16-MHz Crystal
        10. 6.2.2.10 GPADC
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Community Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.6 Electrical Characteristics: LDO Regulator

Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input filtering capacitance (C29, C30, C31, C32, C33, C34) Connected from LDOx_IN to GND. Shared input tank capacitance (depending on platform requirements) 0.6 2.2 µF
Output filtering capacitance (C35, C36, C37, C38, C45, C46, C47)(4) Connected from LDOx_OUT to GND (Except LDO9) 0.6 2.2 2.7 µF
LDO9 Output filtering capacitance (C44)(4) Connected from LDO9_OUT to GND 0.6 2.2 2.7 µF
Connected from LDO9_OUT to GND. LDO9 configured in BYPASS MODE (LDO9_CTRL.LDO_PYPASS_EN = 1) 0.6 1 1.2
CESR Filtering capacitor ESR < 100 kHz 20 100 600 mΩ
1 MHz ≤ f ≤ 10 MHz 1 10 20 mΩ
VLDOx Input voltage, LDOx LDO1, LDO2 0.9 V ≤ VO ≤ 2.15 V 1.2 VVCC1 V
2.2 V ≤ VO ≤ 3.3 V 1.2 5.25
LDOLN, LDO3, LDO4 0.9 V ≤ VO ≤ 2.15 V 1.75 VVCC1
2.2 V ≤ VO ≤ 3.3 V 1.75 5.25
LDO9 0.9 V ≤ VO ≤ 1.75 V 1.75 VVCC1
1.8 V ≤ VO ≤ 3.3 V 1.75 5.25
Bypass Mode 1.75 3.6
VLDOUSB1 Input voltage, LDOUSB1 LDOUSB – From LDOUSB_IN1 0.9 V ≤ VO ≤ 2.15 V 3.6 VVCC1 V
2.2 V ≤ VO ≤ 3.3 V 3.6 5.25
VLDOUSB2 Input voltage, LDOUSB2 LDOUSB – From LDOUSB_IN2 0.9 V ≤ VO ≤ 2.15 V 4.3 VVCC1 V
2.2 V ≤ VO ≤ 3.3 V 4.3 5.25
VI(VCC1) Input voltage, VCC1 VCC1 – Used for internal power supply 3.135 3.8 5.25 V
VO(LDOx) LDO output voltage programmable(1) (except LDOVRTC and LDOVANA) VO(LDOx) < VLDOx – VDROPOUT(LDOx) 0.9 3.3 V
Step size 50 mV
TDCOV(LDOx) Total DC output voltage accuracy, including voltage references, DC load/line regulations, process and temperature All LDOs except LDO3, LDO4, LDOVANA, and LDOVRTC 0.99 × VO(LDOx) –0.014 1.006 × VO(LDOx) + 0.014 V
LDO3, LDO4: IO = 200 mA 0.99 × VO(LDOx) –0.014 1.006 × VO(LDOx) + 0.014
LDO3, LDO4: 200 mA < IO ≤ 300 mA 0.99 × VOUT(LDOx) – 0.018 1.006 × VOUT(LDOx) + 0.018
LDOVRTC_OUT 1.726 1.8 1.85
LDOVANA_OUT 2.002 2.093 2.119
VDROPOUT(LDOx) Dropout voltage(2) LDO1, LDO2: IO = IOmax 150 mV
LDO3, LDO4: IO = 200 mA 290
LDO3, LDO4: IO = IOmax 550
LDO9: IO = IOmax 230
LDOLN: IO = IOmax 150
LDOLN: IO = 100 mA (Functional, not low-noise performance) 290
LDOUSB – From LDOUSB_IN1: IO = IOmax 200
LDOUSB – From LDOUSB_IN2: IO = IOmax 900
VDROPOUT(LDOx) Dropout voltage, internal LDOs LDOVRTC, LDOVANA: IO = IOmax 150 mV
IO(LDOx) Output current LDO1, LDO2 300 mA
LDO3, LDO4 300
LDO9, LDOLN 50
LDOUSB 100
IO(LDOx_int) Output current, internal LDOs LDOVANA 10 mA
LDOVRTC 25
LDO inrush current LDO1, LDO2 500 mA
IL(LDOx) LDO current limitation LDO1, LDO2 380 600 1800 mA
LDO3, LDO4 400 650 1300
LDO9 120 200 400
LDOUSB 120 250 600
LDOLN 150 325 740
LDOVANA 100 250 400
LDOVRTC 55 250 400
ΔVO(ΔVI)(DC) DC load regulation, ΔVO LDO1, LDO2: IO = 0 to IOmax at pin 4 16 mV
LDO3, LDO4: 0 to 200 mA at pin 4 14
LDO3, LDO4: IO = 0 to IOmax at pin 4 18
All other LDOs: IO = 0 to IOmax at pin 4 14
ΔVO(DVI)(DC) DC line regulation, except VRTC,
ΔVO / VO 		VI = VImin to VImax, IO = IOmax 0.1% 0.2%
VSYS = VSYSmin to VSYSmax, IO = IOmax. VI constant (LDO preregulated), VO ≤ 2.2 V 0.3% 0.75%
DC line regulation on LDOVRTC, ΔVO/VO VSYS = VSYSmin to VSYSmax, IO = IOmax 1%
Bypass resistance of LDO9 VI ≥ 2.7 V, programmed to BYPASS 4.2 Ω
ton Turnon time IO = 0, VO = 0.1 V up to VOmin 100 500 µs
toff Turnoff time (except VRTC ) IO = 0, VO down to 10% × VO 250 500 μs
RDIS Pulldown discharge resistance at LDO output, except LDOVRTC OFF mode, pull down enabled and LDO disabled. Also applies to bypass mode 30 125 Ω
Power-supply ripple rejection, LDO1, LDO2 ƒ = 217 Hz, IO = IOmax 55 90 dB
ƒ = 50 kHz, IO = IOmax 28 45
ƒ = 1 MHz, IO = IOmax 25 35
Power-supply ripple rejection, LDO3, LDO4,LDO9, LDOUSB LDO9, LDOUSB: ƒ = 217 Hz, IO = IOmax 55 90 dB
LDO3, LDO4: ƒ = 217 Hz, IO = IOmax 50 60
LDO3, LDO4: ƒ = 217 Hz, IO = 200 mA 55 90
All other LDOs: ƒ = 50 kHz, IO = IOmax 20 45
All other LDOs: ƒ = 1 MHz, IO = IOmax 20 35
Power-supply ripple rejection, LDOLN ƒ = 217 Hz, IO = IOmax 55 90 dB
ƒ = 50 kHz, IO = IOmax 25 45
ƒ = 1 MHz, IO = IOmax 25 35
IQ(off) Quiescent-current off mode For all LDOs, T = 27°C 0.1 µA
For all LDOs, T ≥ 85°C 0.2
IQ(on) Quiescent-current LDO ON mode IL = 0 mA (LDO1, LDO2), 0.9 V ≤ VO ≤ 3.3 V, VO(LDOx) < VLDOx – VDROPOUT(LDOx) 39 70 µA
IL = 0 mA (LDO3, LDO4, LDO9), VO(LDOx) < VLDOx – VDROPOUT(LDOx) 36 47
IL = 0 mA (LDOLN) , VO ≤ 1.8 V, VO(LDOx) < VLDOx – VDROPOUT(LDOx) 140 190
IL = 0 mA (LDOLN) , VO > 1.8 V, VO(LDOx) < VLDOx – VDROPOUT(LDOx) 180 210
IL = 0 mA (LDOUSB) – IN1, VO(LDOx) < VLDOx – VDROPOUT(LDOx) 45 65
IL = 0 mA (LDOUSB) – IN2, VO(LDOx) < VLDOx – DV(LDOx) 18 25
αQ Quiescent current coefficient, LDO ON mode(3) IO < 100 µA 4%
100 µA ≤ IO < 1 mA 2%
IO ≥ 1 mA 1%
ΔVO(ΔIO)(T) Transient load regulation ΔVO All LDOs except LDO3, LDO4, LDO9, LDOLN: ON mode, IO = 10 mA to IOmax / 2, tr = tf = 1 µs –25 25 mV
LDO9, LDOLN: ON mode, IO = 1 mA to IOmax /2, tr = tf = 1 µs –25 25
LDO3, LDO4: ON mode, IO = 10 mA to 100 mA, tr = tf = 1 µs –25 25
LDO3, LDO4: ON mode, IO = 10 mA to IOmax / 2, tr = tf = 1 µs –40 25
ON mode, IO = 100 µA to IOmax / 2, tr = tf = 1 µs –50 33
ΔVO(ΔVI)(T) Transient line regulation, ΔVO / VO VI step = 600 mVPP, tr = tf = 10 µs 0.25% 0.5%
VSYS step = 600 mVPP, tr = tf = 10 µs. VI constant (LDO preregulated), VO ≤ 2.2 V 0.8% 1.6%
Noise (except LDOLN) 100 Hz < ƒ ≤ 10 kHz 5000 8000 nV/√Hz
10 kHz < ƒ ≤ 100 kHz 1250 2500
100 kHz < ƒ ≤ 1 MHz 150 300
ƒ > 1 MHz 250 500
Noise (LDOLN) 100 Hz < ƒ ≤ 5 kHz, IO = 50 mA, VO ≤ 1.8 V 400 500 nV/√Hz
5 kHz < ƒ ≤ 400 kHz, IO = 50 mA, VO ≤ 1.8 V 62 125
400 kHz < ƒ ≤ 10 MHz, IO = 50 mA, VO ≤ 1.8 V 25 50
Ripple LDO1, LDO2, ripple (from internal charge pump) 5 mVPP
(1) LDO output voltages are programmed separately.
(2) VDROPOUT(LDOx) = VI – VO, where VO = VOnom – 2%
(3) IQO = IQ(on) + αQ × IO
(4) Additional information about how this parameter is specified is located in Section 6.2.2.