SLVSCJ5A December   2015  – June 2016 TPS7H3301-SP


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VO Sink and Source Regulator
      2. 7.3.2 Reference Input (VDDQSNS)
      3. 7.3.3 Reference Output (VTTREF)
      4. 7.3.4 EN ControL (EN)
      5. 7.3.5 Power-Good Function (PGOOD)
      6. 7.3.6 VO Current Protection
      7. 7.3.7 VIN UVLO Protection
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. VIN/VDD Capacitor
        2. VLDO Input Capacitor
        3. VTT Output Capacitor
        4. VTTSNS Connection
        5. Low VIN Applications
        6. S3 and Pseudo-S5 Support
        7. Tracking Startup and Shutdown
        8. Output Tolerance Consideration for VTT DIMM Applications
        9. LDO Design Guidelines
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 5962R14288(1):
    • Radiation Hardness Assurance (RHA) Qualified to Total Ionizing Dose (TID) 100 krad(Si)
    • Single Event Latch-Up (SEL), Single Event Gate Rupture (SEGR), Single Event Burnout (SEB) Immune to LET = 65 MeV-cm2/mg (See Radiation Report for Details)
    • SET, SEFI, SEU Immune to 65 MeV-cm2/mg (See Radiation Report for Details)
  • Supports DDR, DDR2, DDR3, DDR3LP, and DDR4 Termination Applications and is Compliant to JEDEC Standards
  • Input Voltage: Supports a 2.5-V and 3.3-V Rail(2)
  • Separate Low-Voltage Input (VLDOIN) Down to
    .9 V for Improved Power Efficiency(2)
  • 3-A Sink and Source Termination Regulator Includes Droop Compensation
  • Enable Input and Power-Good Output for Power Supply Sequencing
  • VTT Termination Regulator
    • Output Voltage Range: 0.5 to 1.75 V
    • 3-A Sink and Source Current
    • ±20-mV Accuracy
  • Integrated Precision Voltage Divider Network With Sense Input
  • Remote Sensing (VOSNS)
  • VTTREF Buffered Reference
    • VDDQ/2 ±1% Accuracy
    • ±10-mA Sink and Source Current
  • Undervoltage Lockout (UVLO), and Overcurrent Limit (OCL) Functionality Integrated

2 Applications

  • Single Board Computers, Solid-State Recorders, and Payload Applications Where DDR, DDR2, DDR3, and Low-Power DDR3 and DDR4 Memory are Used
  • Ultra-Fast Transient Power Applications
  • Available in Military (–55°C to 125°C) Temperature Range
  • Engineering Evaluation (/EM) Components are Available(3)

3 Description

The TPS7H3301-SP is a TID and SEE radiation-hardened double data rate (DDR) 3-A termination regulator with built-in VTTREF buffer. The regulator is specifically design to provide a complete, compact, low-noise solution for space DDR termination applications such as single board computers, solid state recorders, and payload processing.

The TPS7H3301-SP supports and is compliant to DDR, DDR2, DDR3, DDR4, and associated low-power JEDEC specifications. The fast transient response of the TPS7H3301-SP VTT regulator allows for a very stable supply during read/write conditions. . During transients, the fast tracking feature of the VTTREF supply minimizes any voltage offset between VTT and VTTREF. To enable simple power sequencing, both an enable input and a power-good output (PGOOD) have been integrated into the TPS7H3301-SP. The PGOOD output is open-drain so it can be tied to multiple open-drain outputs to monitor when all supplies have come into regulation. The enable signal can also be used to discharge VTT during suspend to RAM (S3) power down mode.

Device Information(1)

TPS7H3301-SP CFP (16) 9.60 mm × 11.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.
  2. Applicable to DDR2, DDR3, DDR3L and DDR4. For DDR, input voltage = 3.3-V nominal. VIN is 2.95 to 3.5 V for DDR1 and VLDOIN > VTT for all DDRs.
    For DDR2 3-A load condition, VIN is 2.45 to 3.5 V.
    VIN headroom: VIN_MIN ≥ VTT + 1.5 V.
  3. These units are intended for engineering evaluation only. They are processed to a noncompliant flow (that is, no burn-in, and so forth) and are tested to a temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance over the full MIL specified temperature range of –55°C to 125°C or operating life.

Standard DDR Application

TPS7H3301-SP ddr_app2_slvscj5.gif

4 Revision History

Changes from * Revision (December 2015) to A Revision

  • Changed title of data sheetGo
  • Added new RHA device featuresGo
  • Deleted soft start feature statementGo
  • Deleted built-in VREF statementGo
  • Deleted misplaced pin functionGo
  • Changed absolute maximum rating for EN pin to 3.6 VGo
  • Deleted specification for PG pin sink currentGo
  • Deleted specification for peak output currentGo
  • Deleted unnecessary graphs from the Typical Characteristics sectionGo
  • Changed typo for VTTREF disabling lower threshold from 0.375 to 0.76 VGo
  • Edited content to reflect there is no built-in soft start and added details regarding tracking at startupGo