SLVSE03 April   2019 TPS929120-Q1

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Bias and Power
        1. 7.3.1.1 Power Supply (SUPPLY)
        2. 7.3.1.2 5-V Low-Drop-Out Linear Regulator (VLDO)
        3. 7.3.1.3 Undervoltage Lockout (UVLO) and Power-On-Reset (POR)
        4. 7.3.1.4 Programmable Low Supply Warning
      2. 7.3.2 Constant Current Output
        1. 7.3.2.1 Reference Current With External Resistor (REF)
        2. 7.3.2.2 64-Step Programmable High-Side Constant-Current Output
      3. 7.3.3 PWM Dimming
        1. 7.3.3.1 PWM Dimming Frequency
        2. 7.3.3.2 PWM Generator
        3. 7.3.3.3 Linear Brightness Control
        4. 7.3.3.4 Exponential Brightness Control
        5. 7.3.3.5 External Clock Input for PWM Generator (CLK)
        6. 7.3.3.6 External PWM Input (PWM0 and PWM1)
      4. 7.3.4 On-chip 8-bit Analog-to-Digital Converter (ADC)
      5. 7.3.5 Diagnostic and Protection in Normal State
        1. 7.3.5.1  Fault Masking
        2. 7.3.5.2  Supply Undervoltage Lockout Diagnostics in Normal State
        3. 7.3.5.3  Low-Supply Warning Diagnostics in Normal State
        4. 7.3.5.4  Reference Diagnostics in Normal State
        5. 7.3.5.5  Pre-Thermal Warning and Overtemperature Protection in Normal State
        6. 7.3.5.6  Communication Loss Diagnostic in Normal State
        7. 7.3.5.7  LED Open-Circuit Diagnostics in Normal State
        8. 7.3.5.8  LED Short-circuit Diagnostics in Normal State
        9. 7.3.5.9  On-Demand Off-State Invisible Diagnostics
        10. 7.3.5.10 On-Demand Off-State Single-LED Short-Circuit (SS) Diagnostics
        11. 7.3.5.11 Automatic Single-LED Short-Circuit (AutoSS) Detection in Normal State
        12. 7.3.5.12 EEPROM CRC Error in Normal State
      6. 7.3.6 Diagnostic and Protection in Fail-Safe States
        1. 7.3.6.1 Fault Masking
        2. 7.3.6.2 Supply UVLO Diagnostics in Fail-Safe States
        3. 7.3.6.3 Low-supply Warning Diagnostics in Fail-Safe states
        4. 7.3.6.4 Reference Diagnostics at Fail-Safe States
        5. 7.3.6.5 Overtemperature Protection in Fail-Safe State
        6. 7.3.6.6 LED Open-circuit Diagnostics in Fail-Safe State
        7. 7.3.6.7 LED Short-circuit Diagnostics in Fail-safe State
        8. 7.3.6.8 EEPROM CRC Error in Fail-safe State
    4. 7.4 Device Functional Modes
      1. 7.4.1 POR State
      2. 7.4.2 Initialization State
      3. 7.4.3 Normal State
      4. 7.4.4 Fail-Safe States
      5. 7.4.5 Program State
      6. 7.4.6 Programmable Output Failure State
      7. 7.4.7 ERR Output
    5. 7.5 Programming
      1. 7.5.1 FlexWire Protocol
        1. 7.5.1.1 Protocol Overview
        2. 7.5.1.2 UART Interface Address Setting
        3. 7.5.1.3 Status Response
        4. 7.5.1.4 Synchronization Byte
        5. 7.5.1.5 Device Address Byte
        6. 7.5.1.6 Register Address Byte
        7. 7.5.1.7 Data Frame
        8. 7.5.1.8 CRC Frame
        9. 7.5.1.9 Burst Mode
      2. 7.5.2 Registers Lock
      3. 7.5.3 All Registers CRC Check
      4. 7.5.4 EEPROM Programming
        1. 7.5.4.1 Chip Selection by Pulling REF Pin High
        2. 7.5.4.2 Chip Selection by ADDR Pins configuration
        3. 7.5.4.3 EEPROM Register Access and Burn
        4. 7.5.4.4 EEPROM Program State Exit
        5. 7.5.4.5 Reading Back EEPROM
    6. 7.6 Register Maps
      1. 7.6.1 FullMap Registers
        1. 7.6.1.1   IOUT0 Register (Offset = 0x0) [reset = X]
          1. Table 16. IOUT0 Register Field Descriptions
        2. 7.6.1.2   IOUT1 Register (Offset = 0x1) [reset = X]
          1. Table 17. IOUT1 Register Field Descriptions
        3. 7.6.1.3   IOUT2 Register (Offset = 0x2) [reset = X]
          1. Table 18. IOUT2 Register Field Descriptions
        4. 7.6.1.4   IOUT3 Register (Offset = 0x3) [reset = X]
          1. Table 19. IOUT3 Register Field Descriptions
        5. 7.6.1.5   IOUT4 Register (Offset = 0x4) [reset = X]
          1. Table 20. IOUT4 Register Field Descriptions
        6. 7.6.1.6   IOUT5 Register (Offset = 0x5) [reset = X]
          1. Table 21. IOUT5 Register Field Descriptions
        7. 7.6.1.7   IOUT6 Register (Offset = 0x6) [reset = X]
          1. Table 22. IOUT6 Register Field Descriptions
        8. 7.6.1.8   IOUT7 Register (Offset = 0x7) [reset = X]
          1. Table 23. IOUT7 Register Field Descriptions
        9. 7.6.1.9   IOUT8 Register (Offset = 0x8) [reset = X]
          1. Table 24. IOUT8 Register Field Descriptions
        10. 7.6.1.10  IOUT9 Register (Offset = 0x9) [reset = X]
          1. Table 25. IOUT9 Register Field Descriptions
        11. 7.6.1.11  IOUT10 Register (Offset = 0xA) [reset = X]
          1. Table 26. IOUT10 Register Field Descriptions
        12. 7.6.1.12  IOUT11 Register (Offset = 0xB) [reset = X]
          1. Table 27. IOUT11 Register Field Descriptions
        13. 7.6.1.13  PWM0 Register (Offset = 0x20) [reset = X]
          1. Table 28. PWM0 Register Field Descriptions
        14. 7.6.1.14  PWM1 Register (Offset = 0x21) [reset = X]
          1. Table 29. PWM1 Register Field Descriptions
        15. 7.6.1.15  PWM2 Register (Offset = 0x22) [reset = X]
          1. Table 30. PWM2 Register Field Descriptions
        16. 7.6.1.16  PWM3 Register (Offset = 0x23) [reset = X]
          1. Table 31. PWM3 Register Field Descriptions
        17. 7.6.1.17  PWM4 Register (Offset = 0x24) [reset = X]
          1. Table 32. PWM4 Register Field Descriptions
        18. 7.6.1.18  PWM5 Register (Offset = 0x25) [reset = X]
          1. Table 33. PWM5 Register Field Descriptions
        19. 7.6.1.19  PWM6 Register (Offset = 0x26) [reset = X]
          1. Table 34. PWM6 Register Field Descriptions
        20. 7.6.1.20  PWM7 Register (Offset = 0x27) [reset = X]
          1. Table 35. PWM7 Register Field Descriptions
        21. 7.6.1.21  PWM8 Register (Offset = 0x28) [reset = X]
          1. Table 36. PWM8 Register Field Descriptions
        22. 7.6.1.22  PWM9 Register (Offset = 0x29) [reset = X]
          1. Table 37. PWM9 Register Field Descriptions
        23. 7.6.1.23  PWM10 Register (Offset = 0x2A) [reset = X]
          1. Table 38. PWM10 Register Field Descriptions
        24. 7.6.1.24  PWM11 Register (Offset = 0x2B) [reset = X]
          1. Table 39. PWM11 Register Field Descriptions
        25. 7.6.1.25  PWML0 Register (Offset = 0x40) [reset = 0xF]
          1. Table 40. PWML0 Register Field Descriptions
        26. 7.6.1.26  PWML1 Register (Offset = 0x41) [reset = 0xF]
          1. Table 41. PWML1 Register Field Descriptions
        27. 7.6.1.27  PWML2 Register (Offset = 0x42) [reset = 0xF]
          1. Table 42. PWML2 Register Field Descriptions
        28. 7.6.1.28  PWML3 Register (Offset = 0x43) [reset = 0xF]
          1. Table 43. PWML3 Register Field Descriptions
        29. 7.6.1.29  PWML4 Register (Offset = 0x44) [reset = 0xF]
          1. Table 44. PWML4 Register Field Descriptions
        30. 7.6.1.30  PWML5 Register (Offset = 0x45) [reset = 0xF]
          1. Table 45. PWML5 Register Field Descriptions
        31. 7.6.1.31  PWML6 Register (Offset = 0x46) [reset = 0xF]
          1. Table 46. PWML6 Register Field Descriptions
        32. 7.6.1.32  PWML7 Register (Offset = 0x47) [reset = 0xF]
          1. Table 47. PWML7 Register Field Descriptions
        33. 7.6.1.33  PWML8 Register (Offset = 0x48) [reset = 0xF]
          1. Table 48. PWML8 Register Field Descriptions
        34. 7.6.1.34  PWML9 Register (Offset = 0x49) [reset = 0xF]
          1. Table 49. PWML9 Register Field Descriptions
        35. 7.6.1.35  PWML10 Register (Offset = 0x4A) [reset = 0xF]
          1. Table 50. PWML10 Register Field Descriptions
        36. 7.6.1.36  PWML11 Register (Offset = 0x4B) [reset = 0xF]
          1. Table 51. PWML11 Register Field Descriptions
        37. 7.6.1.37  CONF_EN0 Register (Offset = 0x50) [reset = 0x0]
          1. Table 52. CONF_EN0 Register Field Descriptions
        38. 7.6.1.38  CONF_EN1 Register (Offset = 0x51) [reset = 0x0]
          1. Table 53. CONF_EN1 Register Field Descriptions
        39. 7.6.1.39  CONF_DIAGEN0 Register (Offset = 0x54) [reset = X]
          1. Table 54. CONF_DIAGEN0 Register Field Descriptions
        40. 7.6.1.40  CONF_DIAGEN1 Register (Offset = 0x55) [reset = X]
          1. Table 55. CONF_DIAGEN1 Register Field Descriptions
        41. 7.6.1.41  CONF_MISC0 Register (Offset = 0x56) [reset = X]
          1. Table 56. CONF_MISC0 Register Field Descriptions
        42. 7.6.1.42  CONF_MISC1 Register (Offset = 0x57) [reset = X]
          1. Table 57. CONF_MISC1 Register Field Descriptions
        43. 7.6.1.43  CONF_MISC2 Register (Offset = 0x58) [reset = X]
          1. Table 58. CONF_MISC2 Register Field Descriptions
        44. 7.6.1.44  CONF_MISC3 Register (Offset = 0x59) [reset = X]
          1. Table 59. CONF_MISC3 Register Field Descriptions
        45. 7.6.1.45  CONF_MISC4 Register (Offset = 0x5A) [reset = X]
          1. Table 60. CONF_MISC4 Register Field Descriptions
        46. 7.6.1.46  CONF_MISC5 Register (Offset = 0x5B) [reset = X]
          1. Table 61. CONF_MISC5 Register Field Descriptions
        47. 7.6.1.47  CLR Register (Offset = 0x60) [reset = 0x0]
          1. Table 62. CLR Register Field Descriptions
        48. 7.6.1.48  CONF_LOCK Register (Offset = 0x61) [reset = 0xF]
          1. Table 63. CONF_LOCK Register Field Descriptions
        49. 7.6.1.49  CONF_MISC6 Register (Offset = 0x62) [reset = 0x0]
          1. Table 64. CONF_MISC6 Register Field Descriptions
        50. 7.6.1.50  CONF_MISC7 Register (Offset = 0x63) [reset = 0x0]
          1. Table 65. CONF_MISC7 Register Field Descriptions
        51. 7.6.1.51  CONF_MISC8 Register (Offset = 0x64) [reset = 0x0]
          1. Table 66. CONF_MISC8 Register Field Descriptions
        52. 7.6.1.52  CONF_MISC9 Register (Offset = 0x65) [reset = 0x0]
          1. Table 67. CONF_MISC9 Register Field Descriptions
        53. 7.6.1.53  FLAG0 Register (Offset = 0x70) [reset = 0x3]
          1. Table 68. FLAG0 Register Field Descriptions
        54. 7.6.1.54  FLAG1 Register (Offset = 0x71) [reset = X]
          1. Table 69. FLAG1 Register Field Descriptions
        55. 7.6.1.55  FLAG2 Register (Offset = 0x72) [reset = X]
          1. Table 70. FLAG2 Register Field Descriptions
        56. 7.6.1.56  FLAG3 Register (Offset = 0x73) [reset = 0x0]
          1. Table 71. FLAG3 Register Field Descriptions
        57. 7.6.1.57  FLAG4 Register (Offset = 0x74) [reset = 0x0]
          1. Table 72. FLAG4 Register Field Descriptions
        58. 7.6.1.58  FLAG5 Register (Offset = 0x75) [reset = 0x0]
          1. Table 73. FLAG5 Register Field Descriptions
        59. 7.6.1.59  FLAG7 Register (Offset = 0x77) [reset = 0xEF]
          1. Table 74. FLAG7 Register Field Descriptions
        60. 7.6.1.60  FLAG8 Register (Offset = 0x78) [reset = X]
          1. Table 75. FLAG8 Register Field Descriptions
        61. 7.6.1.61  FLAG11 Register (Offset = 0x7B) [reset = 0x0]
          1. Table 76. FLAG11 Register Field Descriptions
        62. 7.6.1.62  FLAG12 Register (Offset = 0x7C) [reset = 0x0]
          1. Table 77. FLAG12 Register Field Descriptions
        63. 7.6.1.63  FLAG13 Register (Offset = 0x7D) [reset = 0x0]
          1. Table 78. FLAG13 Register Field Descriptions
        64. 7.6.1.64  FLAG14 Register (Offset = 0x7E) [reset = 0x0]
          1. Table 79. FLAG14 Register Field Descriptions
        65. 7.6.1.65  EEPI0 Register (Offset = 0x80) [reset = 0x3F]
          1. Table 80. EEPI0 Register Field Descriptions
        66. 7.6.1.66  EEPI1 Register (Offset = 0x81) [reset = 0x3F]
          1. Table 81. EEPI1 Register Field Descriptions
        67. 7.6.1.67  EEPI2 Register (Offset = 0x82) [reset = 0x3F]
          1. Table 82. EEPI2 Register Field Descriptions
        68. 7.6.1.68  EEPI3 Register (Offset = 0x83) [reset = 0x3F]
          1. Table 83. EEPI3 Register Field Descriptions
        69. 7.6.1.69  EEPI4 Register (Offset = 0x84) [reset = 0x3F]
          1. Table 84. EEPI4 Register Field Descriptions
        70. 7.6.1.70  EEPI5 Register (Offset = 0x85) [reset = 0x3F]
          1. Table 85. EEPI5 Register Field Descriptions
        71. 7.6.1.71  EEPI6 Register (Offset = 0x86) [reset = 0x3F]
          1. Table 86. EEPI6 Register Field Descriptions
        72. 7.6.1.72  EEPI7 Register (Offset = 0x87) [reset = 0x3F]
          1. Table 87. EEPI7 Register Field Descriptions
        73. 7.6.1.73  EEPI8 Register (Offset = 0x88) [reset = 0x3F]
          1. Table 88. EEPI8 Register Field Descriptions
        74. 7.6.1.74  EEPI9 Register (Offset = 0x89) [reset = 0x3F]
          1. Table 89. EEPI9 Register Field Descriptions
        75. 7.6.1.75  EEPI10 Register (Offset = 0x8A) [reset = 0x3F]
          1. Table 90. EEPI10 Register Field Descriptions
        76. 7.6.1.76  EEPI11 Register (Offset = 0x8B) [reset = 0x3F]
          1. Table 91. EEPI11 Register Field Descriptions
        77. 7.6.1.77  EEPP0 Register (Offset = 0xA0) [reset = 0xFF]
          1. Table 92. EEPP0 Register Field Descriptions
        78. 7.6.1.78  EEPP1 Register (Offset = 0xA1) [reset = 0xFF]
          1. Table 93. EEPP1 Register Field Descriptions
        79. 7.6.1.79  EEPP2 Register (Offset = 0xA2) [reset = 0xFF]
          1. Table 94. EEPP2 Register Field Descriptions
        80. 7.6.1.80  EEPP3 Register (Offset = 0xA3) [reset = 0xFF]
          1. Table 95. EEPP3 Register Field Descriptions
        81. 7.6.1.81  EEPP4 Register (Offset = 0xA4) [reset = 0xFF]
          1. Table 96. EEPP4 Register Field Descriptions
        82. 7.6.1.82  EEPP5 Register (Offset = 0xA5) [reset = 0xFF]
          1. Table 97. EEPP5 Register Field Descriptions
        83. 7.6.1.83  EEPP6 Register (Offset = 0xA6) [reset = 0xFF]
          1. Table 98. EEPP6 Register Field Descriptions
        84. 7.6.1.84  EEPP7 Register (Offset = 0xA7) [reset = 0xFF]
          1. Table 99. EEPP7 Register Field Descriptions
        85. 7.6.1.85  EEPP8 Register (Offset = 0xA8) [reset = 0xFF]
          1. Table 100. EEPP8 Register Field Descriptions
        86. 7.6.1.86  EEPP9 Register (Offset = 0xA9) [reset = 0xFF]
          1. Table 101. EEPP9 Register Field Descriptions
        87. 7.6.1.87  EEPP10 Register (Offset = 0xAA) [reset = 0xFF]
          1. Table 102. EEPP10 Register Field Descriptions
        88. 7.6.1.88  EEPP11 Register (Offset = 0xAB) [reset = 0xFF]
          1. Table 103. EEPP11 Register Field Descriptions
        89. 7.6.1.89  EEPM0 Register (Offset = 0xC0) [reset = 0x0]
          1. Table 104. EEPM0 Register Field Descriptions
        90. 7.6.1.90  EEPM1 Register (Offset = 0xC1) [reset = 0x0]
          1. Table 105. EEPM1 Register Field Descriptions
        91. 7.6.1.91  EEPM2 Register (Offset = 0xC2) [reset = 0xFF]
          1. Table 106. EEPM2 Register Field Descriptions
        92. 7.6.1.92  EEPM3 Register (Offset = 0xC3) [reset = 0xF]
          1. Table 107. EEPM3 Register Field Descriptions
        93. 7.6.1.93  EEPM4 Register (Offset = 0xC4) [reset = 0xFF]
          1. Table 108. EEPM4 Register Field Descriptions
        94. 7.6.1.94  EEPM5 Register (Offset = 0xC5) [reset = 0xF]
          1. Table 109. EEPM5 Register Field Descriptions
        95. 7.6.1.95  EEPM6 Register (Offset = 0xC6) [reset = 0x0]
          1. Table 110. EEPM6 Register Field Descriptions
        96. 7.6.1.96  EEPM7 Register (Offset = 0xC7) [reset = 0xA7]
          1. Table 111. EEPM7 Register Field Descriptions
        97. 7.6.1.97  EEPM8 Register (Offset = 0xC8) [reset = 0x3]
          1. Table 112. EEPM8 Register Field Descriptions
        98. 7.6.1.98  EEPM9 Register (Offset = 0xC9) [reset = 0x0]
          1. Table 113. EEPM9 Register Field Descriptions
        99. 7.6.1.99  EEPM10 Register (Offset = 0xCA) [reset = 0x0]
          1. Table 114. EEPM10 Register Field Descriptions
        100. 7.6.1.100 EEPM11 Register (Offset = 0xCB) [reset = 0x0]
          1. Table 115. EEPM11 Register Field Descriptions
        101. 7.6.1.101 EEPM15 Register (Offset = 0xCF) [reset = 0x23]
          1. Table 116. EEPM15 Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Smart Rear Lamp With Distributed LED drivers
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • AEC-Q100-qualified for automotive applications:
    • Temperature grade 1: –40°C to +125°C, TA
  • 12-channel precision high-side current output:
    • Supply voltage 4.5 V to 40 V
    • Up to 75 mA channel current set by resistor
    • 2-Bit global, 6-bit independent current setting
    • High current accuracy < ±5% at 5 mA to 75 mA
    • High current accuracy < ±10% at 1 mA
    • Low voltage drop 500 mV at 50 mA
    • 12-Bit independent PWM dimming
    • Programmable PWM frequency up to 20 kHz
    • Linear and exponential dimming method
  • FlexWire control interface
    • Up to 1-MHz clock frequency
    • Maximum 16 devices on one FlexWire bus
    • 5-V LDO output to supply CAN transceiver
  • Diagnostic and protection:
    • Programmable fail-safe state
    • LED open-circuit detection
    • LED short-circuit detection
    • Single-LED short-circuit diagnostic
    • Programmable low-supply detection
    • Open-drain ERR for fault indication
    • Watchdog and CRC for FlexWire interface
    • 8-Bit ADC for pin voltage measurement
    • Overtemperature protection