SLWS230E September   2011  – December 2015 TRF3765

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 4WI Timing: Write Operation
    7. 6.7 Readback 4WI Timing
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Lock Detect
      2. 7.3.2 LO Divider
      3. 7.3.3 Selecting the VCO and VCO Frequency Control
      4. 7.3.4 External VCO
    4. 7.4 Device Functional Modes
      1. 7.4.1 VCO_TEST_MODE
      2. 7.4.2 Readback Mode
      3. 7.4.3 Integer and Fractional Mode Selection
      4. 7.4.4 PLL Architecture
        1. 7.4.4.1 Selecting PLL Divider Values
        2. 7.4.4.2 Setup Example for Integer Mode
        3. 7.4.4.3 Setup Example for Fractional Mode
      5. 7.4.5 Fractional Mode Setup
    5. 7.5 Register Maps
      1. 7.5.1 PLL 4WI Registers
        1. 7.5.1.1 Register 1
          1. 7.5.1.1.1 CAL_CLK_SEL[3..0]
          2. 7.5.1.1.2 ICP[4..0]
        2. 7.5.1.2 Register 2
          1. 7.5.1.2.1 PLL_DIV <1.0>
          2. 7.5.1.2.2 VCOSEL_MODE
        3. 7.5.1.3 Register 3
        4. 7.5.1.4 Register 4
        5. 7.5.1.5 Register 5
        6. 7.5.1.6 Register 6
      2. 7.5.2 Readback from the Internal Register Banks
        1. 7.5.2.1 Register 0 Write
          1. 7.5.2.1.1 Register 0 Read
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedures
        1. 8.2.2.1 Power Supply
        2. 8.2.2.2 Loop Filter
        3. 8.2.2.3 Reference Clock
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The TRF3765 device features a four-wire serial programming interface (4WI) that controls an internal 32-bit shift register. There are a total of three signals that must be applied: the clock (CLOCK, pin 4), the serial data (DATA, pin 3); and the latch enable (STROBE, pin 5).

The serial data (DB0-DB31) are loaded least significant bit (LSB) first, and read on the rising edge of CLOCK. STROBE is asynchronous to the CLOCK signal, at its rising edge, the data in the shift register are loaded into the selected internal register. Figure 1 shows the timing for the 4WI. 4WI Timing: Write Operation lists the 4WI timing for the write operation.

7.2 Functional Block Diagram

TRF3765 fbd_lws230.gif

7.3 Feature Description

7.3.1 Lock Detect

The lock detect signal is generated in the phase frequency detector by comparing the VCO target phase against the VCO actual phase. When the two compared phase signals remain aligned for several clock cycles, an internal signal goes high. The precision of this comparison is controlled through the LD_ANA_PREC bits. This internal signal is then averaged and compared against a reference voltage to generate the LD signal. The number of averages used is controlled through LD_DIG_PREC. Therefore, when the VCO is frequency locked, LD is high. When the VCO frequency is not locked, LD may pulse high or exhibit periodic behavior.

By default, the internal lock detect signal is made available on the LD pin. Register bits MUX_CTRL_n can be used to control a multiplexer to output other diagnostic signals on the LD output. The LD control signals are shown in Table 2. Table 3 shows the LD Control Signal Mode settings.

Table 2. LD Control Signals

ADJUSTMENT REGISTER BITS BIT ADDRESSING
Lock detect precision LD_ANA_PREC_0 Reg4B19
Unlock detect precision LD_ANA_PREC_1 Reg4B20
LD averaging count LD_DIG_PREC Reg4B24
Diagnostic output MUX_CTRL_n Reg6B[18..16]

Table 3. LD Control Signal Mode Settings

CONDITION RECOMMENDED SETTINGS
Integer mode LD_ANA_PREC_0 = 0
LD_ANA_PREC_1 = 0
LD_DIG_PREC = 0
Fractional mode LD_ANA_PREC_0 = 1
LD_ANA_PREC_1 = 1
LD_DIG_PREC = 0

7.3.2 LO Divider

The LO divider is shown in Figure 66. It frequency divides the VCO output. Only one of the dividers operates at a time, and the appropriate output is selected by a mux. DIVn bits are controlled through LO_DIV_SEL_n. The output is buffered and provided on output pins LOn_OUT_P and LOn_OUT_N. Outputs are phase-locked but not phase-matched. The output level is controlled through BUFOUT_BIAS.

TRF3765 ai_lo_div_lws230.gif Figure 66. LO Divider

LO_DIV_IB determines the bias level for the divider blocks. The SPEEDUP control is used to bypass a stabilization resistor and reach the final bias level faster after a change in the divider selection. SPEEDUP should be disabled during normal operation.

7.3.3 Selecting the VCO and VCO Frequency Control

To achieve a broad frequency tuning range, the TRF3765 includes four VCOs. Each VCO is connected to a bank of coarse tuning capacitors that determine the valid operating frequency of each VCO. For any given frequency setting, the appropriate VCO and capacitor array must be selected.

The device contains logic that automatically selects the appropriate VCO and capacitor bank. Set bit EN_CAL to initiate the calibration algorithm. During the calibration process, the device selects a VCO and a tuning capacitor state such that VTUNE matches the reference voltage set by VCO_CAL_REF_n. Accuracy of the resulting tuning word is increased through bits CAL_ACC_n at the expense of increased calibration time. A calibration begins immediately when EN_CAL is set; as a result, all registers must contain valid values before a calibration is initiated.

The calibration logic is driven by a CAL_CLK clock derived from the phase frequency detector frequency scaled according to the setting in CAL_CLK_SEL. Faster CAL_CLK frequencies enable faster calibrations, but the logic is limited to clock frequencies up to 600 kHz. The flag R_SAT_ERR is evaluated during the calibration process to indicate calibration counter overflow errors, which occur if CAL_CLK runs too quickly. If R_SAT_ERR is set during a calibration, the resulting calibration is not valid and CAL_CLK_SEL must be used to slow the CAL_CLK. CAL_CLK frequencies should not be set below 0.05 MHz. Reference clock frequency is usually limited by the calibration logic. fREF × CAL_CLK_SEL scaling factor > 0.01 MHz and fREF/(CAL_CLK_SEL scaling factor × fPFD) < 8000 are required. For example, with fREF = 61.44 MHz, fPFD = 30.72 MHz and CAL_CLK_SEL at 1/128, 61.44/128 = 0.5 > 0.01 and 61.44/(30.72 × 1/128) = 256 < 8000.

When VCOSEL_MODE is 0, the device automatically selects both the VCO and capacitor bank within 46 CAL_CLK cycles. When VCOSEL_MODE is 1, the device uses the VCO selected in VCO_SEL_0 and VCO_SEL_1 and automatically selects the capacitor array within 34 CAL_CLK cycles. The VCO and capacitor array settings that result from a calibration cannot be read from the VCO_SEL_n and VCO_TRIM_n bits in Registers 2 and 7. These settings can only be read from Register 0.

Automatic calibration can be disabled by setting CAL_BYPASS to 1. In this manual calibration mode, the VCO is selected through register bits VCO_SEL_n, while the capacitor array is selected through register bits VCO_TRIM_n. Calibration modes are summarized in Table 4. After calibration is complete, the PLL is released from calibration mode and reaches phase lock.

Table 4. VCO Calibration Modes

CAL_BYPASS VCOSEL_MODE MAX CYCLES CAL_CLK VCO CAPACITOR ARRAY
0 0 46 Automatic
0 1 34 VCO_SEL_n Automatic
1 don't care N/A VCO_SEL_n VCO_TRIM_n

During the calibration process, the TRF3765 scans through many frequencies. RF and LO outputs should be disabled until calibration is complete. At power-up, the RF and LO output are disabled by default. Once a calibration has been performed at a given frequency setting, the calibration remains valid over all operating temperature conditions.

7.3.4 External VCO

An external LO or VCO signal may be applied. EN_EXTVCO powers the input buffer and selects the buffered external signal instead of an internal VCO. Dividers, phase-frequency detector, and charge pump remain enabled and may be used to control VTUNE or an external VCO. NEG_VCO must correspond to the sign of the external VCO tuning characteristic. EXT_VCO_CTRL = 1 asserts a logic 1 output level at the corresponding output pin. This configuration can be used to enable or disable the external VCO circuit or module.

7.4 Device Functional Modes

7.4.1 VCO_TEST_MODE

Setting VCO_TEST_MODE forces the currently selected VCO to the edge of its frequency range by disconnecting the charge pump input from the phase detector and loop filter, and forcing its output high or low. The upper or lower edge of the VCO range is selected through COUNT_MODE_MUX_SEL.

VCO_TEST_MODE also reports the value of a frequency counter in COUNT, which can be read back in Register 0. COUNT reports the number of digital N divider cycles in the PLL, directly related to the period of fN, that occur during each CAL_CLK cycle. Counter operation is initiated through the bit EN_CAL. Table 5 summarizes the settings for VCO_TEST_MODE.

Table 5. VCO_TEST_MODE Settings

VCO_TEST_MODE COUNT_MODE_MUX_SEL VCO OPERATION REGISTER 0 B[30..13]
0 Don't care Normal B[30..24] = undefined
B[23..22] = VCO_SEL selected during autocal
B21 = undefined
B[20..15] = VCO_TRIM selected during autocal
B[14..13] = undefined
1 0 Max frequency B[30..13] = Max frequency counter
1 1 Min frequency B[30..13] = Min frequency counter

7.4.2 Readback Mode

Register 0 functions as a readback register. The TRF3765 implements the capability to read back the content of any serial programming interface register by initializing Register 0.

Each read-back operation consists of two phases: a write followed by the actual reading of the internal data. This sequence is described in the timing diagram (see Figure 2). During the write phase, a command is sent to TRF3765 Register 0 to set it to readback mode and to specify which register is to be read. In the proper reading phase, at each rising clock edge, the internal data are transferred to the READBACK pin where it can be read at the following falling edge (LSB first). The first clock after the latch enable STROBE, pin 5, goes high (that is, the end of the write cycle) is idle and the following 32 clock pulses transfer the internal register contents to the READBACK pin (pin 6).

7.4.3 Integer and Fractional Mode Selection

The PLL is designed to operate in either Integer mode or Fractional mode. If the desired local oscillator (LO) frequency is an integer multiple of the phase frequency detector (PFD) frequency, fPFD, then Integer mode can be selected. The normalized in-band phase noise floor in Integer mode is lower than in Fractional mode. In Integer mode, the feedback divider is an exact integer, and the fraction is zero. While operating in Integer mode, the register bits corresponding to the fractional control are don’t care.

In Fractional mode, the feedback divider fractional portion is non-zero on average. With 25-bit fractional resolution, RF stepsize fPFD/225 is less than 1 Hz with a fPFD up to 33 MHz. The appropriate fractional control bits in the serial register must be programmed.

7.4.4 PLL Architecture

Figure 67 shows a diagram of the PLL loop.

TRF3765 bd_pll_loop_lws230.gif Figure 67. PLL Architecture

The output frequency is given by Equation 1:

Equation 1. TRF3765 q_fvco_output_fqcy_lws230.gif

The rate at which phase comparison occurs is fREF/RDIV. In Integer mode, the fractional setting is ignored and Equation 2 is applied.

Equation 2. TRF3765 q_fvco_ignored_lws230.gif

The feedback divider block consists of a programmable RF divider, a prescaler divider, and an NF divider. The prescaler can be programmed as either a 4/5 or an 8/9 prescaler. The NF divider includes an A counter and an M counter.

7.4.4.1 Selecting PLL Divider Values

Operation of the PLL requires the LO_DIV_SEL, RDIV, PLL_DIV_SEL, NINT, and NFRAC bits to be calculated. The LO or mixer frequency is related to fVCO according to divide-by-1/-2/-4/-8 blocks and the operating range of fVCO.

  1. LO_DIV_SEL
  2. TRF3765 q_lo_div_sel_matrix_lws230.gif

    Therefore:

    TRF3765 q_fvco_lo_div_sel_lws230.gif
  3. PLL_DIV_SEL
  4. Given fVCO, select the minimum value for PLL_DIV_SEL so that the programmable RF divider limits the input frequency into the prescaler block, fPM, to a maximum of 3000 MHz.

    PLL _ DIV _ SEL = min(1, 2, 4) such that fPM ≤ 3000 MHz

    This calculation can be restated as Equation 3.

    Equation 3. TRF3765 q_pll_ceiling_lws230.gif

    Higher values of fPFD correspond to better phase noise performance in Integer mode or Fractional mode. fPFD, along with PLL_DIV_SEL, determines the fVCO stepsize in Integer mode. Therefore, in Integer mode, select the maximum fPFD that allows for the required RF stepsize, as shown by Equation 4.

    Equation 4. TRF3765 q_pfd_fvco_lws230.gif

    In Fractional mode, a small RF stepsize is accomplished through the Fractional mode divider. A large fPFD should be used to minimize the effects of fractional controller noise in the output spectrum. In this case, fPFD may vary according to the reference clock and fractional spur requirements; for example, fPFD = 20 MHz.

  5. RDIV, NINT, NFRAC, PRSC_SEL
  6. TRF3765 q_rdiv_lws230.gif
    TRF3765 q_nint_floor_lws230.gif
    TRF3765 q_nfrac_floor_lws230.gif

    The P/(P+1) programmable prescaler is set to 8/9 or 4/5 through the PRSC_SEL bit. To allow proper fractional control, set PRSC_SEL according to Equation 5.

    Equation 5. TRF3765 q_prsc_sel_lws230.gif

    The PRSC_SEL limit at NINT < 75 applies to Fractional mode with third-order modulation. In Integer mode, the PRSC_SEL = 8/9 should be used with NINT as low as 72. The divider block accounts for either value of PRSC_SEL without requiring NINT or NFRAC to be adjusted. Then, calculate the maximum frequency to be input to the digital divider at fN. Use the lower of the possible prescaler divide settings, P = (4,8), as shown by Equation 6.

    Equation 6. TRF3765 q_fn_max_lws230.gif

    Verify that the frequency into the digital divider, fN, is less than or equal to 375 MHz. If fN exceeds 375 MHz, choose a larger value for PLL_DIV_SEL and recalculate fPFD, RDIV, NINT, NFRAC, and PRSC_SEL.

7.4.4.2 Setup Example for Integer Mode

Suppose the following operating characteristics are desired for Integer mode operation:

  • fREF = 40 MHz (reference input frequency)
  • Step at RF = 2 MHz (RF channel spacing)
  • fRF = 1600 MHz (RF frequency)

The VCO range is 2400 MHz to 4800 MHz. Therefore:

  • LO_DIV_SEL = 2
  • fVCO = LO_DIV_SEL × 1600 MHz = 3200 MHz

To keep the frequency of the prescaler below 3000 MHz:

  • PLL_DIV_SEL = 2

The desired stepsize at RF is 2 MHz, so:

  • fPFD = 2 MHz
  • fVCO, stepsize = PLL_DIV_SEL × fPFD = 4 MHz

Using the reference frequency along with the required fPFD gives:

  • RDIV = 20
  • NINT = 800

NINT ≥ 75; therefore, select the 8/9 prescaler.

where

This example shows that Integer mode operation gives sufficient resolution for the required stepsize.

7.4.4.3 Setup Example for Fractional Mode

Suppose the following operating characteristics are desired for Fractional mode operation:

  • fREF = 40 MHz (reference input frequency)
  • Step at RF = 5 MHz (RF channel spacing)
  • fRF = 1,600,000,045 Hz (RF frequency)

The VCO range is 2400 MHz to 4800 MHz. Therefore:

  • LO_DIV_SEL = 2
  • fVCO = LO_DIV_SEL × 1,600,000,045 Hz = 3,200,000,090 Hz

To keep the frequency of the prescaler below 3000 MHz:

  • PLL_DIV_SEL = 2

Using a typical fPFD of 20 MHz:

  • RDIV = 20
  • NINT = 80
  • NFRAC = 75

NINT ≥ 75; therefore, select the 8/9 prescaler.

where

The actual frequency at RF is:

  • fRF = 1600000044.9419 Hz

For a frequency error of –0.058 Hz.

7.4.5 Fractional Mode Setup

Optimal operation of the PLL in Fractional mode requires several additional register settings. Recommended values are listed in Register Maps. Optimal performance may require tuning the MOD_ORD, ISOURCE_SINK, and ISOURCE_TRIM values according to the chosen frequency band.

Table 6. Fractional Mode Register Settings

REGISTER BIT REGISTER ADDRESSING RECOMMENDED VALUE
EN_ISOURCE Reg4B18 1
EN_DITH Reg4B25 1
MOD_ORD Reg4B[27..26] B[27..26] = [10]
DITH_SEL Reg4B28 0
DEL_SD_CLK Reg4B[30..29] B[30..29] = [10]
EN_FRAC Reg4B31 1
EN_LD_ISOURCE Reg5B31 0
ISOURCE_SINK Reg6B19 0
ISOURCE_TRIM Reg6B[22..20] B[22..20] = [100] or [111]; see Typical Characteristics
ICPDOUBLE Reg1B26 0

7.5 Register Maps

7.5.1 PLL 4WI Registers

7.5.1.1 Register 1

Figure 68. PLL 4WI Register 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSV VCO CAL CLK
DIV/MULT
CP
DOUBLE
CHARGE PUMP CURRENT VCO NEG REF INV RSV REF CLOCK DIV
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFERENCE CLOCK DIVIDER REGISTER ADDRESS

Table 7. PLL 4WI Register 1

Bit Field Reset Value Description
Bit0 ADDR_0 1 Register address bits
Bit1 ADDR_1 0
Bit2 ADDR_2 0
Bit3 ADDR_3 1
Bit4 ADDR_4 0
Bit5 RDIV_0 1 13-bit Reference Divider value
Bit6 RDIV_1 0
Bit7 RDIV_2 0
Bit8 RDIV_3 0
Bit9 RDIV_4 0
Bit10 RDIV_5 0
Bit11 RDIV_6 0
Bit12 RDIV_7 0
Bit13 RDIV_8 0
Bit14 RDIV_9 0
Bit15 RDIV_10 0
Bit16 RDIV_11 0
Bit17 RDIV_12 0
Bit18 RSV 0 Reserved
Bit19 REF_INV 0 Invert Reference Clock polarity; 1 = use falling edge
Bit20 NEG_VCO 1 VCO polarity control; 1= negative slope (negative KV)
Bit21 ICP_0 0 Program Charge Pump dc current, ICP
1.94 mA, B[25..21] = [00 000]
0.65 mA, B[25..21] = [11 111]
0.97 mA, default value, B[25..21] = [01 010]
Bit22 ICP_1 1
Bit23 ICP_2 0
Bit24 ICP_3 1
Bit25 ICP_4 0
Bit26 ICPDOUBLE 0 1 = Set ICP to double the current
Bit27 CAL_CLK_SEL_0 0 Multiplication or division factor to create VCO calibration clock from PFD frequency
Fastest clock, B[25..21] = [00 000]
Slowest clock, B[25..21] = [11 111]
Bit28 CAL_CLK _SEL_1 0
Bit29 CAL_CLK _SEL_2 0
Bit30 CAL_CLK _SEL_3 1
Bit31 RSV 0 Reserved

7.5.1.1.1 CAL_CLK_SEL[3..0]

Set the frequency divider value used to derive the VCO calibration clock from the phase detector frequency. Table 8 shows the calibration clock scale factors.

Table 8. Calibration Clock Scale Factors

CAL_CLK_SEL SCALING FACTOR
1111 1/128
1110 1/64
1101 1/32
1100 1/16
1011 1/8
1010 1/4
1001 1/2
1000 1
0110 2
0101 4
0100 8
0011 16
0010 32
0001 64
0000 128

7.5.1.1.2 ICP[4..0]

Set the charge pump current. Table 9 lists the charge pump current settings.

Table 9. Charge Pump Current Settings

ICP[4..0] CURRENT (mA)
00 000 1.94
00 001 1.76
00 010 1.62
00 011 1.49
00 100 1.38
00 101 1.29
00 110 1.21
00 111 1.14
01 000 1.08
01 001 1.02
01 010 0.97
01 011 0.92
01 100 0.88
01 101 0.84
01 110 0.81
01 111 0.78
10 000 0.75
10 001 0.72
10 010 0.69
10 011 0.67
10 100 0.65
10 101 0.63
10 110 0.61
10 111 0.59
11 000 0.57
11 001 0.55
11 010 0.54
11 011 0.52
11 100 0.51
11 101 0.5
11 110 0.48
11 111 0.47

7.5.1.2 Register 2

Figure 69. PLL 4WI Register 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN CAL CAL ACCURACY VCO SEL MODE VCO SELECT RSV RSV PRE-
SCALER SELECT
PLL DIVIDER SETTING N-DIVIDER VALUE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
N-DIVIDER VALUE REGISTER ADDRESS

Table 10. PLL 4WI Register 2

Bit Field Reset Value Description
Bit0 ADDR_0 0 Register address bits
Bit1 ADDR_1 1
Bit2 ADDR_2 0
Bit3 ADDR_3 1
Bit4 ADDR_4 0
Bit5 NINT_0 0 PLL N-divider division setting
Bit6 NINT_1 0
Bit7 NINT_2 0
Bit8 NINT_3 0
Bit9 NINT_4 0
Bit10 NINT_5 0
Bit11 NINT_6 0
Bit12 NINT_7 1
Bit13 NINT_8 0
Bit14 NINT_9 0
Bit15 NINT_10 0
Bit16 NINT_11 0
Bit17 NINT_12 0
Bit18 NINT_13 0
Bit19 NINT_14 0
Bit20 NINT_15 0
Bit21 PLL_DIV_SEL0 1 Select division ratio of divider in front of prescaler
Bit22 PLL_DIV_SEL1 0
Bit23 PRSC_SEL 1 Set prescaler modulus (0 → 4/5; 1 → 8/9)
Bit24 RSV 0 Reserved
Bit25 RSV 0 Reserved
Bit26 VCO_SEL_0 0 Selects between the four integrated VCOs
00 = lowest frequency VCO; 11= highest frequency VCO
Bit27 VCO_SEL_1 1
Bit28 VCOSEL_MODE 0 Single VCO auto-calibration mode (1 = active)
Bit29 CAL_ACC_0 0 Error count during the cap array calibration
Recommended programming [00].
Bit30 CAL_ACC_1 0
Bit31 EN_CAL 0 Execute a VCO frequency auto-calibration. Set to 1 to initiate a calibration. Resets automatically.

7.5.1.2.1 PLL_DIV <1.0>

Select division ratio of divider in front of prescaler, according to Table 11.

Table 11. PLL_DIV Selection

PLL_DIV FREQUENCY DIVIDER
00 1
01 2
10 4

7.5.1.2.2 VCOSEL_MODE

When VCOSEL_MODE is set to 1, the cap array calibration is executed on the VCO selected through bits VCO_SEL[1:0].

7.5.1.3 Register 3

Figure 70. PLL 4WI Register 3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSV RSV FRACTIONAL N-DIVIDER VALUE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRACTIONAL N-DIVIDER VALUE REGISTER ADDRESS

Table 12. PLL 4WI Register 3

Bit Field Reset Value Description
Bit0 ADDR_0 1 Register address bits
Bit1 ADDR_1 1
Bit2 ADDR_2 0
Bit3 ADDR_3 1
Bit4 ADDR_4 0
Bit5 NFRAC<0> 0 Fractional PLL N divider value
0 to 0.99999
Bit6 NFRAC<1> 0
Bit7 NFRAC<2> 0
Bit8 NFRAC<3> 0
Bit9 NFRAC<4> 0
Bit10 NFRAC<5> 0
Bit11 NFRAC<6> 0
Bit12 NFRAC<7> 0
Bit13 NFRAC<8> 0
Bit14 NFRAC<9> 0
Bit15 NFRAC<10> 0
Bit16 NFRAC<11> 0
Bit17 NFRAC<12> 0
Bit18 NFRAC<13> 0
Bit19 NFRAC<14> 0
Bit20 NFRAC<15> 0
Bit21 NFRAC<16> 0
Bit22 NFRAC<17> 0
Bit23 NFRAC<18> 0
Bit24 NFRAC<19> 0
Bit25 NFRAC<20> 0
Bit26 NFRAC<21> 0
Bit27 NFRAC<22> 0
Bit28 NFRAC<23> 0
Bit29 NFRAC<24> 0
Bit30 RSV 0 Reserved
Bit31 RSV 0 Reserved

7.5.1.4 Register 4

Figure 71. PLL 4WI Register 4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN FRACT MODE ΔΣ MOD CONTROLS ΔΣ MOD ORDER PLL TESTS CONTROL EXT VCO
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POWER-DOWN OUTPUT BUFFERS POWER-DOWN PLL BLOCKS PD PLL REGISTER ADDRESS

Table 13. PLL 4WI Register 4

Bit Field Reset Value Description
Bit0 ADDR_0 0 Register address bits
Bit1 ADDR_1 0
Bit2 ADDR_2 1
Bit3 ADDR_3 1
Bit4 ADDR_4 0
Bit5 PWD_PLL 0 Power-down all PLL blocks (1 = off)
Bit6 PWD_CP 0 When 1, charge pump is off
Bit7 PWD_VCO 0 When 1, VCO is off
Bit8 PWD_VCOMUX 0 Power-down the four VCO mux blocks (1 = off)
Bit9 PWD_DIV124 0 Power-down programmable RF divider in PLL feedback path (1 = off)
Bit10 PWD_PRESC 0 Power-down programmable prescaler (1 = off)
Bit11 PWD_LO_DIV 1 Power-down LO divider block (1 = off)
Bit12 PWD_BUFF_1 1 Power-down LO output buffer 1 (1 = off)
Bit13 PWD_BUFF_2 1 Power-down LO output buffer 2 (1 = off)
Bit14 PWD_BUFF_3 1 Power-down LO output buffer 3 (1 = off)
Bit15 PWD_BUFF_4 1 Power-down LO output buffer 4 (1 = off)
Bit16 EN_EXTVCO 0 Enable external VCO input buffer (1 = enabled)
Bit17 EXT_VCO_CTRL 0 Can be used to enable/disable an external VCO through pin EXTVCO_CTRL (1 = high).
Bit18 EN_ISOURCE 0 Enable offset current at Charge Pump output (to be used in Fractional mode only; 1 = on).
Bit19 LD_ANA_PREC_0 0 Control precision of analog lock detector
1 = low; 0 = high
Bit20 LD_ANA_PREC_1 0
Bit21 CP_TRISTATE_0 0 Set the charge pump output into 3-state mode.
Normal, B[22..21] = [00]
Down, B[22..21] = [01]
Up, B[22..21] = [10]
3-state, B[22..21] = [11]
Bit22 CP_TRISTATE_1 0
Bit23 SPEEDUP 0 Speed up PLL block by bypassing bias stabilizer capacitors.
Bit24 LD_DIG_PREC 0 Lock detector precision
(increases sampling time if set to 1)
Bit25 EN_DITH 1 Enable ΔΣ modulator dither (1 = on)
Bit26 MOD_ORD_0 0 ΔΣ modulator order (1 through 4). Not used in Integer mode.
First order, B[27..26] = [00]
Second order, B[27..26] = [01]
Third order, B[27..26] = [10]
Fourth order, B[27..26] = [11]
Bit27 MOD_ORD_1 1
Bit28 DITH_SEL 0 Select dither mode for ΔΣ modulator
(0 = pseudo-random; 1 = constant)
Bit29 DEL_SD_CLK_0 0 ΔΣ modulator clock delay. Not used in Integer mode.
Min delay = 00; Max delay = 11
Bit30 DEL_SD_CLK_1 1
Bit31 EN_FRAC 0 Enable Fractional mode (1 = fractional enabled)

7.5.1.5 Register 5

Figure 72. PLL 4WI Register 5
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN_LD
ISRC
RSV VCO BIAS VOLTAGE VCOMUX AMPL VCO CAL REF BIAS SEL RSV RSV OUTBUF BIAS VCOMUX BIAS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VCOBUF BIAS VCO CURRENT PLL_R_TRIM VCO_R_TRIM REGISTER ADDRESS

Table 14. PLL 4WI Register 5

Bit Field Reset Value Description
Bit0 ADDR_0 1 Register address bits
Bit1 ADDR_1 0
Bit2 ADDR_2 1
Bit3 ADDR_3 1
Bit4 ADDR_4 0
Bit5 VCOBIAS_RTRIM_0 0 VCO bias resistor trimming.
Recommended programming [100].
Bit6 VCOBIAS_RTRIM_1 0
Bit7 VCOBIAS_RTRIM_2 1
Bit8 PLLBIAS_RTRIM_0 0 PLL bias resistor trimming.
Recommended programming [10].
Bit9 PLLBIAS_RTRIM_1 1
Bit10 VCO_BIAS_0 0 VCO bias reference current.
300 μA, B[13..10] = [00 00]
600 μA, B[13..10] = [11 11]
Bias current varies directly with reference current
Recommended programming:
400 μA, B[13..10] = [0101] with VCC_TK = 3.3 V
600 μA, B[13..10] = [1111] with VCC_TK = 5.0V
Bit11 VCO_BIAS_1 0
Bit12 VCO_BIAS_2 0
Bit13 VCO_BIAS_3 1
Bit14 VCOBUF_BIAS_0 0 VCO buffer bias reference current.
300 μA, B[15..14] = [00]
600 μA, B[15..14] = [11]
Bias current varies directly with reference current
Recommended programming [10]
Bit15 VCOBUF _BIAS_1 1
Bit16 VCOMUX_BIAS_0 0 VCO muxing buffer bias reference current.
300 μA, B[17..16] = [00]
600 μA, B[17..16] = [11]
Bias current varies directly with reference current
Recommended programming [10]
Bit17 VCOMUX _BIAS_1 1
Bit18 BUFOUT_BIAS_0 1 PLL output buffer bias reference current.
300 μA, B[19..18] = [00]
600 μA, B[19..18] = [11]
Bias current varies directly with reference current
Bit19 BUFOUT_BIAS_1 0
Bit20 RSV 0 Reserved
Bit21 RSV 1 Reserved
Bit22 VCO_CAL_IB 0 Select bias current type for VCO calibration circuitry
0 = PTAT; 1 = constant over temperature. Recommended programming [0].
Bit23 VCO_CAL_REF_0 0 VCO calibration reference voltage trimming.
0.9 V, B[25..23] = [000]
1.4 V, B[25..23] = [111]
Recommended programming 1.11 V, B[25..23] = [011]
Bit24 VCO_CAL_REF_1 0
Bit25 VCO_CAL_REF_2 1
Bit26 VCO_AMPL_CTRL_0 0 Adjust the signal amplitude at the VCO mux input.
[00] = maximum voltage swing
[11] = minimum voltage swing
Recommended programming [11]
Bit27 VCO_AMPL_CTRL_1 1
Bit28 VCO_VB_CTRL_0 0 VCO core bias voltage control
1.2 V, B[29..28] = [00]
1.35 V, B[29..28] = [01]
1.5 V, B[29..28] = [10]
1.65 V, B[29..28] = [11]
Recommended programming [01]
Bit29 VCO_VB_CTRL _1 1
Bit30 RSV 0 Reserved
Bit31 EN_LD_ISOURCE 1 Enable monitoring of LD to turn on ISOURCE when in frac-n mode (EN_FRAC=1).
0 = ISOURCE set by EN_ISOURCE
1 = ISOURCE set by LD
Recommended programming [0]

7.5.1.6 Register 6

Figure 73. PLL 4WI Register 6
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VCO BIAS SEL DC OFF REF VCO MUX BIAS LO DIV BIAS LO DIV OFFSET CURRENT ADJUST ISRC SINK MUX CONTROL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAL BYPASS VCO TEST MODE LD MODE VCO CAP ARRAY CONTROL RSV RSV REGISTER ADDRESS

Table 15. PLL 4WI Register 6

Bit Field Reset Value Description
Bit0 ADDR_0 0 Register address bits
Bit1 ADDR_1 1
Bit2 ADDR_2 1
Bit3 ADDR_3 1
Bit4 ADDR_4 0
Bit5 RSV 0 Reserved
Bit6 RSV 0 Reserved
Bit7 VCO_TRIM_0 0 VCO capacitor array control bits; used in manual cal mode
Bit8 VCO_TRIM_1 0
Bit9 VCO_TRIM_2 0
Bit10 VCO_TRIM_3 0
Bit11 VCO_TRIM_4 0
Bit12 VCO_TRIM_5 1
Bit13 EN_LOCKDET 0 Initiate automatic calibration if LD indicates loss of lock.
(1 = Initiate calibration if LD is low)
Bit14 VCO_TEST_MODE 0 Counter mode: measure maximum/minimum frequency of each VCO
Bit15 CAL_BYPASS 0 Bypass of VCO auto-calibration. When 1, VCO_TRIM and VCO_SEL bits are used to select the VCO and the capacitor array setting
Bit16 MUX_CTRL_0 1 Select signal for test output (pin 5, LD).
[000] = Ground
[001] = Lock detector
[010] = NDIV counter output
[011] = Ground
[100] = RDIV counter output
[101] = Ground
[110] = A_counter output
[111] = Logic high
Bit17 MUX_CTRL_1 0
Bit18 MUX_CTRL_2 0
Bit19 ISOURCE_SINK 0 Charge pump offset current polarity. 0 = source
ISOURCE current enabled by EN_ISOURCE.
Recommended programming [0].
Bit20 ISOURCE_TRIM_0 0 Adjust ISOURCE bias current.
Minimum value, ISOURCE_TRIM = 0, B[22..20] = [000]
Maximum value, ISOURCE_TRIM = 7, B[22..20] = [111]
ISOURCE current enabled by EN_ISOURCE.
Bit21 ISOURCE_TRIM_1 0
Bit22 ISOURCE_TRIM_2 1
Bit23 LO_DIV_SEL_0 0 Adjust LO path divider
Divide-by-1, [B24..23] = [00]
Divide-by-2, [B24..23] = [01]
Divide-by-4, [B24..23] = [10]
Divide-by-8, [B24..23] = [11]
Bit24 LO_DIV_SEL_1 0
Bit25 LO_DIV_IB_0 0 Adjust LO divider bias current. [B26..25] =
[00] = 25 μA
[01] = 37.5 μA
[10] = 50 μA
[11] = 62.5 μA
Bit26 LO_DIV_IB_1 0
Bit27 DIV_MUX_REF<0> 0 Sets reference bias current of DIV_MUX buffer when bit 31=1;
[00] = 500 μA
[01] = 400 μA
[10] = 300 μA
[11] = 200 μA
Recommended programming [10]
Bit28 DIV_MUX_REF<1> 1
Bit29 DIV_MUX_OUT<0> 0 Set multiply factor for DIV_MUX_REF current.
x16, B[30..29] = 00
x24, B[30..29] = 01
x32, B[30..29] = 10
x40, B[30..29] = 11
Recommended programming [10]
Bit30 DIV_MUX_OUT<1> 1
Bit31 DIV_MUX_BIAS_OVRD 0 Overrides DIV_MUX auto-bias current control.
When set to 1, DIV_MUX bias current is set by [B30..27].

7.5.2 Readback from the Internal Register Banks

The TRF3765 integrates eight registers: Register 0 (000) to Register 7 (111). Registers 1 through 6 are used to set up and control the TRF3765 functions, Register 7 is used for factory functions, and Register 0 is used for the readback function, as shown in Readback Mode.

Register 0 must be programmed with a specific command that sets the TRF3765 into readback mode and specifies the register to be read, according to the following parameters:

  • Set B[31] to 1 to put TRF3765 into readback mode.
  • Set B[30,28] equal to the address of the register to be read (000 to 111).
  • Set B27 to control the VCO frequency counter in VCO test mode.

7.5.2.1 Register 0 Write

Figure 74. Register 0 Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RB_
ENABLE
RB_REG COUNT_
MODE_
MUX_SEL
N/C
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
N/C REGISTER ADDRESS

Table 16. Register 0 Write

Type Bit Field Reset Value Description
Address Bit0 ADDR<0> 0 Register 0 to be programmed to set the TRF3765 into readback mode.
Bit1 ADDR<1> 0
Bit2 ADDR<2> 0
Bit3 ADDR<3> 1
Bit4 ADDR<4> 0
Data Field Bit5 N/C 0
Bit6 N/C 0
Bit7 N/C 0
Bit8 N/C 0
Bit9 N/C 0
Bit10 N/C 0
Bit11 N/C 0
Bit12 N/C 0
Bit13 N/C 0
Bit14 N/C 0
Bit15 N/C 0
Bit16 N/C 0
Bit17 N/C 0
Bit18 N/C 0
Bit19 N/C 0
Bit20 N/C 0
Bit21 N/C 0
Bit22 N/C 0
Bit23 N/C 0
Bit24 N/C 0
Bit25 N/C 0
Bit26 N/C 0
Bit27 COUNT_MODE_MUX_SEL 0 Select Readback for VCO maximum frequency or minimum frequency.
0 = Maximum
1 = Minimum
Bit28 RB_REG<0> X Three LSBs of the address for the register that is being read
Register 1, B[30..28] = [000]
Register 7, B[30..28] = [111]
Bit29 RB_REG<1> X
Bit30 RB_REG<2> X
Bit31 RB_ENABLE 1 1 → Put the device into readback mode

7.5.2.1.1 Register 0 Read

Figure 75. Register 0 Read
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNT
MODE
MUX_SEL
COUNT11-17 COUNT9-10/VCO_SEL COUNT8/
NU
COUNT0-7/VCO_TRIM
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNT0-7/VCO_TRIM R_SAT_ERR NOT USED CHIP_ID REGISTER ADDRESS
Figure 76. PLL 4WI Register 6

Table 17. Register 0 Read

Bit Field Reset Value Description
Bit0 ADDR_0 0 Register address bits
Bit1 ADDR_1 0
Bit2 ADDR_2 0
Bit3 ADDR_3 1
Bit4 ADDR_4 0
Bit5 CHIP_ID 1
Bit6 NU x
Bit7 NU x
Bit8 NU x
Bit9 NU x
Bit10 NU x
Bit11 NU x
Bit12 R_SAT_ERR x Error flag for calibration speed
Bit13 count_0/NU x B[30..13] = VCO frequency counter high when COUNT_MODE_MUX_SEL = 0 and VCO_TEST_MODE = 1

B[30..13] = VCO frequency counter low when COUNT_MODE_MUX_SEL = 1 and VCO_TEST_MODE = 1

B[20..15] = Autocal results for VCO_TRIM

B[23..22] = Autocal results for VCO_SEL when VCO_TEST_MODE = 0
Bit14 count_1/NU x
Bit15 count_2/VCO_TRIM_0 x
Bit16 count_3/VCO_TRIM_1 x
Bit17 count_4/VCO_TRIM_2 x
Bit18 count_5/VCO_TRIM_3 x
Bit19 count_6/VCO_TRIM_4 x
Bit20 count_7/VCO_TRIM_5 x
Bit21 count_8/NU x
Bit22 count_9/VCO_sel_0 x
Bit23 count_10/VCO_sel_1 x
Bit24 count<11> x
Bit25 count<12> x
Bit26 count<13> x
Bit27 count<14> x
Bit28 count<15> x
Bit29 count<16> x
Bit30 count<17> x
Bit31 COUNT_MODE_MUX_SEL x 0 = Minimum frequency
1 = Maximum frequency