SLUSC82A March   2015  – March 2015 UCC24630

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Start Up and UVLO
      2. 7.3.2 Volt-Sec SR Driver On-Time Control
      3. 7.3.3 CCM Dead Time
      4. 7.3.4 Standby Operation
      5. 7.3.5 Pin Fault Protection
        1. 7.3.5.1 VPC Pin Overvoltage
        2. 7.3.5.2 VPC Pin Open
        3. 7.3.5.3 VSC Pin Open
        4. 7.3.5.4 TBLK Pin Open
        5. 7.3.5.5 VPC and VSC Short to Ground
        6. 7.3.5.6 TBLK Pin Short to Ground
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-Up
      2. 7.4.2 Normal Operation
      3. 7.4.3 Standby Operation
      4. 7.4.4 Conditions to Stop Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 AC-to-DC Adapter, 19.5 V, 65 W
      2. 8.2.2 Design Requirements
      3. 8.2.3 Calculation of Component Values
        1. 8.2.3.1 VPC Input
        2. 8.2.3.2 VSC Input
        3. 8.2.3.3 TBLK Input
      4. 8.2.4 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 VDD Pin
      2. 10.1.2 VPC Pin
      3. 10.1.3 VSC Pin
      4. 10.1.4 GND Pin
      5. 10.1.5 TBLK Pin
      6. 10.1.6 DRV Pin
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Definition of Terms
      2. 12.3   Electrostatic Discharge Caution
      3. 12.4   Glossary
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

In general, try to keep all high current loops as short as possible. Keep all high current/high frequency traces away from other traces in the design. If necessary, high-frequency/high-current traces should be perpendicular to signal traces, not parallel to them. Shielding signal traces with ground traces can help reduce noise pick up. Always consider appropriate clearances between the high-voltage connections and any low-voltage nets.

10.1.1 VDD Pin

The VDD pin must be decoupled to GND with good quality, low ESR, low ESL ceramic bypass capacitors with short traces to the VDD and GND pins. The value of the required capacitance on VDD is determined as shown in Section 7.3 . To eliminate high-frequency ripple current in the SR control circuit, it is recommended to place a small value resistance of 2.2 Ω to 10 Ω between VDD and the converter output voltage.

10.1.2 VPC Pin

The trace between the resistor divider and the VPC pin should be as short as possible to reduce/eliminate possible noise coupling. The lower resistor of the resistor divider network connected to the VPC pin should be returned to GND with short traces. Avoid adding any significant external capacitance to the VPC pin so that there is no delay of signal. If filtering is necessary a recommended maximum capacitance is 10 pF with a lower resistor divider network value of 10 kΩ. Avoid high dV/dt traces close to the VPC pin and connection trace such as the SR MOSFET drain and DRV output.

10.1.3 VSC Pin

The trace between the resistor divider and the VSC pin should be as short as possible to reduce/eliminate possible noise coupling. The lower resistor of the resistor divider network connected to the VSC pin should be returned to GND with short traces. Avoid adding any external capacitance to the VPC pin so that there is no delay of signal. If filtering is necessary a recommended maximum capacitance is 47 pF with a lower resistor divider network value of 50 kΩ. Avoid high dV/dt traces close to the VSC pin and connection trace such as the SR MOSFET drain and DRV output.

10.1.4 GND Pin

The GND pin is the power and signal ground connection for the controller. The effectiveness of the filter capacitors on the signal pins depends upon the integrity of the ground return. Place all decoupling capacitors as close as possible to the device pins with short traces. The device ground and power ground should meet at the output bulk capacitor’s return. Try to ensure that high frequency/high current from the power stage does not go through the signal ground.

10.1.5 TBLK Pin

The programming resistor is placed on TBLK to GND, with short traces. The value may have to be adjusted based on the time delay required. Avoid high dV/dt traces close to the TBLK pin and connection trace such as the SR MOSFET drain and DRV output.

10.1.6 DRV Pin

The track connected to DRV carries high dv/dt signals. Minimize noise pickup by routing the trace to this pin as far away as possible from tracks connected to the device signal inputs, VPC, VSC, and TBLK.

10.2 Layout Example

UCC24630 layout_luub81.gif