SLUSD90C June   2019  – March 2020 UCC256402 , UCC256403 , UCC256404

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Simplified Schematic
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hybrid Hysteretic Control
      2. 8.3.2 Regulated 13-V Supply
      3. 8.3.3 Feedback Chain
        1. 8.3.3.1 Optocoupler Feedback Signal Input and Bias
        2. 8.3.3.2 FB Pin Voltage Clamp
        3. 8.3.3.3 "Pick Lower Value" Block and Soft Start Multiplexer
        4. 8.3.3.4 Pick Higher Block and Burst Mode Multiplexer
        5. 8.3.3.5 VCR Comparators
      4. 8.3.4 Resonant Capacitor Voltage Sensing
      5. 8.3.5 Resonant Current Sensing
      6. 8.3.6 Bulk Voltage Sensing
      7. 8.3.7 Output Voltage Sensing
      8. 8.3.8 High Voltage Gate Driver
        1. 8.3.8.1 Adaptive Dead Time Control
      9. 8.3.9 Protections
        1. 8.3.9.1 ZCS Region Prevention
        2. 8.3.9.2 Over Current Protection (OCP)
        3. 8.3.9.3 Bias Winding Over Voltage Protection (BWOVP)
        4. 8.3.9.4 Input Under Voltage Protection (VINUVP)
        5. 8.3.9.5 Input Over Voltage Protection (VINOVP)
        6. 8.3.9.6 Boot UVLO
        7. 8.3.9.7 RVCC UVLO
        8. 8.3.9.8 Over Temperature Protection (OTP)
    4. 8.4 Device Functional Modes
      1. 8.4.1 High Voltage Start-Up
      2. 8.4.2 X-Capacitor Discharge
      3. 8.4.3 Burst Mode Control
        1. 8.4.3.1 Soft-Start and Burst-Mode Threshold
        2. 8.4.3.2 BMTL/BMTH Ratio Programming
      4. 8.4.4 System State Machine
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  LLC Power Stage Requirements
        2. 9.2.2.2  LLC Gain Range
        3. 9.2.2.3  Select Ln and Qe
        4. 9.2.2.4  Determine Equivalent Load Resistance
        5. 9.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 9.2.2.6  LLC Primary-Side Currents
        7. 9.2.2.7  LLC Secondary-Side Currents
        8. 9.2.2.8  LLC Transformer
        9. 9.2.2.9  LLC Resonant Inductor
        10. 9.2.2.10 LLC Resonant Capacitor
        11. 9.2.2.11 LLC Primary-Side MOSFETs
        12. 9.2.2.12 LLC Rectifier Diodes
        13. 9.2.2.13 LLC Output Capacitors
        14. 9.2.2.14 HV Pin Series Resistors
        15. 9.2.2.15 BLK Pin Voltage Divider
        16. 9.2.2.16 ISNS Pin Differentiator
        17. 9.2.2.17 VCR Pin Capacitor Divider
        18. 9.2.2.18 BW Pin Voltage Divider
        19. 9.2.2.19 Soft Start and Burst Mode Programming
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VCC Pin Capacitor
    2. 10.2 Boot Capacitor
    3. 10.3 RVCC Pin Capacitor
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

High Voltage Gate Driver

LO is the low-side gate driver output. The gate driver is supplied by the 13-V RVCC rail.

The high-side driver module consists of three physical device pins. HB and HS form the positive and negative bias rail, respectively, of the high-side driver, and HO connects to the gate of the upper half-bridge MOSFET.

During periods when the lower half-bridge MOSFET is conducting, HS is shorted to GND via the conducting lower MOSFET. At this time power for the high-side driver is obtained from RVCC via the high voltage diode DBOOT, and capacitor CBOOT is charged to RVCC minus the forward drop on the diode.

During periods when the upper half-bridge MOSFET is conducting, HS is connected to the LLC input voltage rail. At this time the HV diode is reverse biased and the high-side driver is powered by the charge stored in CBOOT.

Both the high-side and low-side gate drivers have under voltage lock out (UVLO) protection. The low-side gate driver UVLO is implemented on RVCC; the high-side gate driver UVLO is implemented on (HB - HS) voltage.

When operating at light load, UCC25640x enters burst mode. During the burst off period, the gate driver enters low power mode to reduce power consumption.

The block diagram of the gate driver is shown in Figure 35.

UCC256402 UCC256403 UCC256404 Fig-04-slusd90.gifFigure 35. Gate Driver Block Diagram