SLUSD90C June   2019  – March 2020 UCC256402 , UCC256403 , UCC256404

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Simplified Schematic
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hybrid Hysteretic Control
      2. 8.3.2 Regulated 13-V Supply
      3. 8.3.3 Feedback Chain
        1. 8.3.3.1 Optocoupler Feedback Signal Input and Bias
        2. 8.3.3.2 FB Pin Voltage Clamp
        3. 8.3.3.3 "Pick Lower Value" Block and Soft Start Multiplexer
        4. 8.3.3.4 Pick Higher Block and Burst Mode Multiplexer
        5. 8.3.3.5 VCR Comparators
      4. 8.3.4 Resonant Capacitor Voltage Sensing
      5. 8.3.5 Resonant Current Sensing
      6. 8.3.6 Bulk Voltage Sensing
      7. 8.3.7 Output Voltage Sensing
      8. 8.3.8 High Voltage Gate Driver
        1. 8.3.8.1 Adaptive Dead Time Control
      9. 8.3.9 Protections
        1. 8.3.9.1 ZCS Region Prevention
        2. 8.3.9.2 Over Current Protection (OCP)
        3. 8.3.9.3 Bias Winding Over Voltage Protection (BWOVP)
        4. 8.3.9.4 Input Under Voltage Protection (VINUVP)
        5. 8.3.9.5 Input Over Voltage Protection (VINOVP)
        6. 8.3.9.6 Boot UVLO
        7. 8.3.9.7 RVCC UVLO
        8. 8.3.9.8 Over Temperature Protection (OTP)
    4. 8.4 Device Functional Modes
      1. 8.4.1 High Voltage Start-Up
      2. 8.4.2 X-Capacitor Discharge
      3. 8.4.3 Burst Mode Control
        1. 8.4.3.1 Soft-Start and Burst-Mode Threshold
        2. 8.4.3.2 BMTL/BMTH Ratio Programming
      4. 8.4.4 System State Machine
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  LLC Power Stage Requirements
        2. 9.2.2.2  LLC Gain Range
        3. 9.2.2.3  Select Ln and Qe
        4. 9.2.2.4  Determine Equivalent Load Resistance
        5. 9.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 9.2.2.6  LLC Primary-Side Currents
        7. 9.2.2.7  LLC Secondary-Side Currents
        8. 9.2.2.8  LLC Transformer
        9. 9.2.2.9  LLC Resonant Inductor
        10. 9.2.2.10 LLC Resonant Capacitor
        11. 9.2.2.11 LLC Primary-Side MOSFETs
        12. 9.2.2.12 LLC Rectifier Diodes
        13. 9.2.2.13 LLC Output Capacitors
        14. 9.2.2.14 HV Pin Series Resistors
        15. 9.2.2.15 BLK Pin Voltage Divider
        16. 9.2.2.16 ISNS Pin Differentiator
        17. 9.2.2.17 VCR Pin Capacitor Divider
        18. 9.2.2.18 BW Pin Voltage Divider
        19. 9.2.2.19 Soft Start and Burst Mode Programming
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VCC Pin Capacitor
    2. 10.2 Boot Capacitor
    3. 10.3 RVCC Pin Capacitor
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Resonant Current Sensing

The ISNS pin is connected to the resonant capacitor using a high voltage capacitor. The capacitor CISNS and the resistor RISNS form a differentiator. The resonant capacitor voltage is differentiated to get the resonant current. The differentiated signal is AC and goes both positive and negative. In order to sense the zero crossing, the signal is level shifted using an op amp adder. The IPolarity comparator detects the direction of the resonant current. IPolarity is checked at LSON and HSON falling edges for ZCS protection, with more details described in ZCS Region Prevention section. The digital state machine implements a blanking time on IPolarity. The IPolarity edges during the first 400 ns of dead time are ignored considering the noise on ISNS pin introduced by the switching node transition.

OCP2 and OCP3 thresholds are based on average input current. To get the average input current, the differentiator output is multiplexed with the high-side switch on signal HSON. When HSON is on, the MUX output is the differentiator output; when HSON is off, the MUX output is 0. The MUX output is then averaged using a low pass filter. The output of the filter is the sensed average input current. Note that the MUX needs to pass through both positive and negative voltages. OCP2 and OCP3 faults have a 2 ms and 50 ms timer respectively. Only when the OCP2/OCP3 comparators output high for continuous 2 ms or 50 ms, will the faults be activated.

OCP1 threshold is set on the peak resonant current. The voltage on the ISNS pin gets compared to OCP1 threshold OCP1Th directly. The peak resonant current is checked once per cycle on the positive half cycle. OCP1 fault is only activated when there are 4 consecutive cycles of OCP1 event detected. During start up, the OCP1 comparator output of the first 15 cycles are ignored.

UCC256402 UCC256403 UCC256404 fig42_sluscu6.gifFigure 32. ISNS Block Diagram